参数资料
型号: PF38F3352LLZDQ0
厂商: INTEL CORP
元件分类: 存储器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA88
封装: 11 X 13 MM, SCSP-88
文件页数: 35/54页
文件大小: 966K
代理商: PF38F3352LLZDQ0
768-Mbit LVQ Family with Asynchronous Static RAM
40
Datasheet
Traditional write, erase, and burst-mode read capabilities of Intel Wireless flash memory.
Simultaneous RWW/RWE operations, enabling a burst read operation in one partition while
simultaneous with program or erase operations in other partitions.
Burst-read across partition boundaries, but not across segment dies within the subsystem.
Note:
User application code is responsible for ensuring that burst-mode reads do not cross into a partition
that is in program or erase mode.
The embedded data segment includes the following features unless specifically noted otherwise:
High Density offerings of up to 512 Mb designated specifically for large embedded data.
Single partition asynchronous page-mode read operation, allowing for a cost-effective ideal
storage format.
Read-while-program or read-while-erase operations can be accomplished with software
through program suspend and erase suspend operations.
17.3
Flash Die Memory Map
The 768-Mbit LVQ Family with Asynchronous Static RAM device is available in several density
and parameter configurations. The memory map is based on the stacking of individual flash die
density options of 128 Mbit or 256 Mbit. The memory map shows individual flash die
configurations and block/partition allocations.
The code segment flash die is made up of 128-Mbit dies or 256-Mbit dies, each containing one
parameter partition and several main partitions.
The 128-Mbit memory array is divided into sixteen 8-Mbit partitions. Each die density contains
one parameter partition and fifteen main partitions. The 8-Mbit top or bottom parameter partition
contains four 16-Kword blocks and seven 64-Kword blocks. Each of the remaining fifteen 8-Mbit
main partitions contains eight 64-Kword blocks.
The 256-Mbit memory array is divided into sixteen 16-Mbit partitions. Each device contains one
parameter partition and fifteen main partitions. The 16-Mbit top or bottom parameter partition
contains four 16-Kword blocks and fifteen 64-Kword blocks. Each of the remaining fifteen 16-
Mbit main partitions contains sixteen 64-Kword blocks.
The data segment flash die density is made up of 128-Mbit dies or 256-Mbit dies, each containing
a single partition architecture made up of four 16-Kword parameter blocks and 64-Kword main
blocks. The memory map and partitioning for various flash die combinations, top and bottom
parameters and are shown in the following tables:
Note:
Only 128-Mbit and 256-Mbit flash die densities are used in three flash die SCSP combinations.
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