参数资料
型号: SDED7-256M-N9T
厂商: SANDISK CORP
元件分类: 存储控制器/管理单元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PBGA115
封装: 12 X 9 MM, 1.20 MM HEIGHT, FBGA-115
文件页数: 39/87页
文件大小: 1675K
代理商: SDED7-256M-N9T
Rev. 1.2
mDOC H3 Registers
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
44
92-DS-1205-10
WAKE_UP_SEL_BIT
Selects the device wake up trigger
0: mDOC H3 CE# is the wakeup trigger.
1: Read access (CE# & OE# assertion) or write access (CE# and WE#
assertion) is the wakeup trigger.
7.3.8
DPD Activation Register
Description:
This 16-bit register is used to put mDOC H3 into Deep Power Down mode.
Address (hex): 9416 (128KB window) / 1416 (8KB window)
Type:
Read / Write
Bit number
D15-D1
D0
Read/Write
R
W
Bit name
RFU
POWER_DN
Reset value
0
POWER_DN
Setting this bit to ‘1’ will put the device to Deep Power Down mode.
7.3.9
DMA Control Register
Description:
This 16-bit register controls the DMA_REQ signal to the host.
Address (hex): 940E (128KB window) / 140E (8KB window)
Type:
Read / Write
Bit number
D15-D9
D8-D4
D3
D2
D1
D0
Read/Write
R
R/W
R
R/W
Bit name
RFU
PULSE_WIDTH RFU
EDGE
DMA_POL
DMA_EN
Reset value
0
4
0
1
0
PULSE_WIDTH
The width of the DMARQ# signal will be:
PULSE_WIDTH * ICMU_CLK (cycle). Maximum 32 ICMU clocks.
Note: If the value is zero then DMARQ# signal will not be asserted.
EDGE
Level or Edge:
0: Level – DMARQ# will be asserted when data is ready and will be de-asserted
before the end of the data according to DMA_PROG_NEG (DMA Negation).
1: Edge – DMARQ# will be generated for the number of clock specified in the
PULSE_WIDTH field.
DMA_POL
DMARQ# polarity:
0: active high
相关PDF资料
PDF描述
SDED7-256M-N9Y FLASH MEMORY DRIVE CONTROLLER, PBGA115
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相关代理商/技术参数
参数描述
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