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| 型号： | SDED7-256M-N9T |
| 厂商： | SANDISK CORP |
| 元件分类： | 存储控制器/管理单元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PBGA115 |
| 封装： | 12 X 9 MM, 1.20 MM HEIGHT, FBGA-115 |
| 文件页数： | 52/87页 |
| 文件大小： | 1675K |
| 代理商： | SDED7-256M-N9T |
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Rev. 1.2
Design Considerations
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
56
92-DS-1205-10
cycle made to mDOC must observe the multiplexed mode protocol. See Section 10 for more
information about the related timing requirements.
specifications for a multiplexed interface.
9.7
Implementing the Interrupt Mechanism
9.7.1
Hardware Configuration
To configure the hardware for working with the interrupt mechanism, the IRQ# ball should be
connected to a host interrupt input.
9.7.2
Software Configuration
IRQ# signal may be used by mDOC H3 to interrupt the host system, provided that device
interrupts are enabled. Interrupts can be enabled or disabled using the flHwConfig DOC Driver
API. For more information see the DOC Driver 1.0 Block Device (BD) Software Developer Kit
(SDK) Developer Guide. When asserted, the IRQ# signal will remain asserted until cleaned
(level only). This cleaning is performed automatically by the DOC Driver as part of the API
(read or write) completion.
mDOC H3 will interrupt the host system in the following cases:
Device is ready to receive a data block (excluding the first) during write operation.
When using DMA transfers:
On completion of block device operation to mDOC H3.
Device is ready to send a data block during a read operation.
9.8
DMA and Burst Operation
mDOC H3 enhances performance using various proprietary techniques among them are
Burst operation to read or write large chunks of data, providing a Burst speed.
DMA operation to release the CPU for other tasks in coordination with the platform’s
DMA controller. This is especially useful during the boot stage. Up to 128KB of data
can be transferred during a DMA operation.
9.8.1
DMA Operation
mDOC H3 provides a DMARQ# output that enables data transfer using the host DMA
controller. During DMA operation, the DMARQ# output is used to notify the host DMA
controller that data is ready to be read or written. mDOC H3 protocol enables such data transfer
up to the maximal size of 128KB per read or write operation.
The DMARQ# output sensitivity is selected by setting the EDGE bit in the DMA Control
register:
1. Edge DMARQ# output pulses to indicate to the DMA controller that a data is ready to be
transferred. The EDGE bit is set to 1 for this mode. The amount of data that will be
transferred corresponds to data block size.
相关PDF资料 |
PDF描述 |
|---|---|
| SDED7-256M-N9Y | FLASH MEMORY DRIVE CONTROLLER, PBGA115 |
| SPMC68336AVFT20 | 32-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP160 |
| SPMC68336GCFT20 | 32-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP160 |
| SC104002VPVR2 | 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP112 |
| S9S12XF512J0MLH | MICROCONTROLLER, QFP64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SDED7-256M-N9Y | 功能描述:IC MDOC H3 256MB FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘 供应商设备封装:8-DFN（2x3） 包装:管件 产品目录页面:1445 (CN2011-ZH PDF) |
| SDED7-512M-NAT | 功能描述:IC MDOC H3 512MB FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘 供应商设备封装:8-DFN（2x3） 包装:管件 产品目录页面:1445 (CN2011-ZH PDF) |
| SDED7-512M-NAY | 功能描述:IC MDOC H3 512MB FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘 供应商设备封装:8-DFN（2x3） 包装:管件 产品目录页面:1445 (CN2011-ZH PDF) |
| SDEG-15P | 制造商:HRS 制造商全称:HRS 功能描述:STRAIGHT/METAL PCB D-SUB |
| SDEG-15P05 | 制造商:HRS 制造商全称:HRS 功能描述:STRAIGHT/METAL PCB D-SUB |
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