参数资料
型号: SDED7-256M-N9T
厂商: SANDISK CORP
元件分类: 存储控制器/管理单元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PBGA115
封装: 12 X 9 MM, 1.20 MM HEIGHT, FBGA-115
文件页数: 43/87页
文件大小: 1675K
代理商: SDED7-256M-N9T
Rev. 1.2
Booting from mDOC H3
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
48
92-DS-1205-10
8.1.1
Asynchronous Boot Mode
Host platforms should use Asynchronous Boot mode when using mDOC H3 as the system boot
device.
During platform initialization, certain CPUs wake up in 32-bit mode and issue instruction fetch
cycles continuously. An Intel PXAxxx CPU, for example, initiates a 16-bit read cycle, but after
the first word is read, it continues to hold CE# and OE# asserted while it increments the address
and reads additional data as a burst.
Once in Asynchronous Boot mode, the CPU can fetch its instruction from the mDOC H3
Programmable Boot Block. After reading from this block and completing the boot, mDOC H3
returns to derive its internal clock signal from the CE#, OE#, and WE# inputs. Please refer to
Section 10 for read timing specifications for Asynchronous Boot mode.
8.1.2
Paged RAM Boot
The Paged RAM Boot feature uses the IPL SRAM as two 1KB sections. The first section
provides constant data, while the other section can be downloaded sequentially with flash data.
One application of this feature is to support Secure Boot requirements. The Paged RAM Boot
feature does not require support of the BUSY# output.
After a hardware or software reset, mDOC H3 initializes the first 2KB of XIP RAM with data
stored in the first 2KB of the pre-programmed IPL. The Paged RAM Boot feature permits 1KB
virtual pages (up to 254KB total) to be downloaded sequentially to the XIP RAM, upon
receiving the proper command sequence. Since the mDOC H3 BUSY# output is not asserted by
a page-load operation, a polling procedure is required to determine when the download is
complete. An XIP operation from the mDOC H3 RAM is not supported during this polling
operation, so it must be executed from system RAM or ROM instead.
When two mDOC H3 devices are cascaded, Paged RAM downloads occur only on the first
mDOC H3 device in the cascaded configuration (device-0).
For more information on booting from mDOC H3 in Paged RAM Boot mode, please contact
your local SanDisk sales office.
相关PDF资料
PDF描述
SDED7-256M-N9Y FLASH MEMORY DRIVE CONTROLLER, PBGA115
SPMC68336AVFT20 32-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP160
SPMC68336GCFT20 32-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP160
SC104002VPVR2 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP112
S9S12XF512J0MLH MICROCONTROLLER, QFP64
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