参数资料
型号: W25Q64FVSSIG
厂商: Winbond Electronics
文件页数: 14/89页
文件大小: 0K
描述: IC SPI FLASH 64MBIT 8SOIC
标准包装: 90
系列: SpiFlash®
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 64M(8M x 8)
速度: 80MHz
接口: SPI 串行
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.209",5.30mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
W25Q64FV
5.2
WRITE PROTECTION
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the W25Q64FV
provides several means to protect the data from inadvertent writes.
5.2.1
Write Protect Features
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Device resets when VCC is below threshold
Time delay write disable after Power-up
Write enable/disable instructions and automatic write disable after erase or program
Software and Hardware (/WP pin) write protection using Status Register
Write Protection using Power-down instruction
Lock Down write protection for Status Register until the next power-up
One Time Program (OTP) write protection for array and Security Registers using Status Register *
* Note: This feature is available upon special order. Please contact Winbond for details.
Upon power-up or at power-down, the W25Q64FV will maintain a reset condition while VCC is below the
threshold value of V WI , (See Power-up Timing and Voltage Levels and Figure 43). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds V WI , all program and erase related instructions are further disabled for a time delay of t PUW . This
includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status
Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until
the VCC-min level and t VSL time delay is reached, and it must also track the VCC supply level at power-
down to prevent adverse command sequence. If needed a pull-up resister on /CS can be used to
accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-
disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting
the Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits.
These settings allow a portion as small as a 4KB sector or the entire memory array to be configured as
read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be
enabled or disabled under hardware control. See Status Register section for further information.
Additionally, the Power-down instruction offers an extra level of write protection as all instructions are
ignored except for the Release Power-down instruction.
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