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参数资料
| 型号： | AD9549ABCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 23/76页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 产品变化通告： | AD9549A Mask Change 22/Oct/2010 |
| 标准包装： | 750 |
| 类型： | 时钟/频率发生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，HSTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 750MHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
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AD9549
Rev. D | Page 3 of 76
REVISION HISTORY
1
2/10—Rev. C to Rev. D
Changes to IAVDD (Pin 19, Pin 23 to Pin 26, Pin 29, Pin 30,
Pin44, Pin 45) Parameter .................................................................4
Changes to Total Power Dissipation Parameter and Added
Endnote 4 ...........................................................................................5
Changes to Pin 59 Description......................................................11
Changes to Direct Digital Synthesizer (DDS) Section ...............20
Changes to Power-Up Section .......................................................42
Changes to Address 0x0002 Default Value (in Table 13) ...........48
Changes to Address 0x0400 and Address 0x40E Default Values
(in Table 13) .....................................................................................52
5/10—Rev. B to Rev. C
Deleted 64-Lead LFCSP (CP-64-1).................................. Universal
Changes to SYSCLK PLL Enabled/Minimum Differential Input
Level Parameter, Table 2 ...................................................................6
Updated Outline Dimensions........................................................74
Changes to Ordering Guide...........................................................74
1/10—Rev. A to Rev. B
Changes to I/O Register Map Section, Introduction and
Table 13.............................................................................................48
Changes to Register 0x0405 to Register 0x0408—Reserved
Section ..............................................................................................70
Added Register 0x0406—Part Version Section...........................71
12/09—Rev. 0 to Rev. A
Added 64-Lead LFCSP (CP-64-7) ................................... Universal
Changes to Total Power Dissipation Parameter............................5
Changes to Serial Port Timing Specifications and
Propagation Delay Parameters ........................................................8
Added Exposed Paddle Notation to Figure 2; Changes to
Table 4...............................................................................................10
Corrected DDS Phase Offset Resolution from 16 Bits to
14 Bits Throughout; Change to Figure 25....................................20
Changes to Phase Lock Detection Section ..................................24
Change to Figure 30........................................................................25
Changes to Loss of Reference and Reference Frequency
Monitor Sections .............................................................................26
Change to Output Frequency Range Control Section ...............32
Change to Figure 46........................................................................36
Changes to Frequency Estimator Section ....................................37
Changes to Programming Sequence Section ..............................42
Changes to Power Supply Partitioning Section...........................43
Change to Serial Control Port Section .........................................44
Changes to Figure 54 ......................................................................46
Added Exposed Paddle Notation to Outline Dimensions and
Changes to Ordering Guide...........................................................74
8/07—Revision 0: Initial Version
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相关代理商/技术参数 |
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| AD9549APCBZ | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
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