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参数资料
| 型号： | AD9549ABCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 67/76页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 产品变化通告： | AD9549A Mask Change 22/Oct/2010 |
| 标准包装： | 750 |
| 类型： | 时钟/频率发生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，HSTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 750MHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
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AD9549
Rev. D | Page 7 of 76
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CMOS Output Driver
(AVDD3/Pin 37) @ 3.3 V
Frequency Range
0.008
150
MHz
See
Figure 14 for maximum toggle rate
Duty Cycle
45
55
65
%
With 20 pF load and up to 150 MHz
Rise Time/Fall Time (20-80%)
3
4.6
ns
With 20 pF load
CMOS Output Driver
(AVDD3/Pin 37) @ 1.8 V
Frequency Range
0.008
40
MHz
See
Figure 13 for maximum toggle rate
Duty Cycle
45
55
65
%
With 20 pF load and up to 40 MHz
Rise Time/Fall Time (20% to 80%)
5
6.8
ns
With 20 pF load
HOLDOVER
Frequency Accuracy
See the
Holdover section
OUTPUT FREQUENCY SLEW LIMITER
Slew Rate Resolution
0.54
111
Hz/sec
P = 216 for minimum; P = 25 for maximum
Slew Rate Range
0
3 × 1016
Hz/sec
P = 216 for minimum; P = 25 for maximum
REFERENCE MONITORS
Loss of Reference Monitor
Operating Frequency Range
7.63 × 103
167 × 106
Hz
Minimum Frequency Error for
Continuous REF Present Indication
16
ppm
fREF = 8 kHz
Minimum Frequency Error for
Continuous REF Present Indication
19
%
fREF = 155 MHz
Maximum Frequency Error for
Continuous REF Lost Indication
32
ppm
fREF = 8 kHz
Maximum Frequency Error for
Continuous REF Lost Indication
35
%
fREF = 155 MHz
Reference Quality Monitor
Operating Frequency Range
0.008
150
MHz
Frequency Resolution (Normalized)
0.2
ppm
fREF = 8 kHz; OOL divider = 65,535 for minimum; OOL
divider = 1 for max (see the
Monitor section)
Frequency Resolution (Normalized)
408
ppm
fREF = 155 MHz; OOL divider = 65,535 for minimum;
OOL divider = 1 for maximum
Validation Timer
See the
Timing Range
32 × 109
137
sec
PIO = 5
Timing Range
65 × 106
2.8 × 105
sec
PIO = 16
DAC OUTPUT CHARACTERISTICS
DCO Frequency Range (1st Nyquist Zone)
10
450
MHz
DPLL loop bandwidth sets lower limit
Output Resistance
50
Single-ended (each pin internally terminated to AVSS)
Output Capacitance
5
pF
Full-Scale Output Current
20
31.7
mA
Range depends on DAC RSET resistor
Gain Error
10
+10
% FS
Output Offset
0.6
μA
Voltage Compliance Range
AVSS
0.50
+0.5
AVSS +
0.50
Outputs not dc-shorted to VSS
DIGITAL PLL
Minimum Open-Loop Bandwidth
0.1
Hz
Dependent on the frequency of REFA/REFB, the DAC
sample rate, and the P-, R-, and S-divider values
Maximum Open-Loop Bandwidth
100
kHz
Dependent on the frequency of REFA/REFB, the DAC
sample rate, and the P-, R-, and S-divider values
Minimum Phase Margin
0
10
Degrees
Dependent on the frequency of REFA/REFB, the DAC
sample rate, and the P-, R-, and S-divider values
Maximum Phase Margin
85
90
Degrees
Dependent on the frequency of REFA/REFB, the DAC
sample rate, and the P-, R-, and S-divider values
PFD Input Frequency Range
~0.008
~24.5
MHz
Feedforward Divider Ratio
1
131,070
1, 2, …, 65,535 or 2, 4, …, 131,070
Feedback Divider Ratio
1
131,070
1, 2, …, 65,535 or 2, 4, …, 131,070
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