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参数资料
| 型号： | AD9549ABCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 59/76页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 产品变化通告： | AD9549A Mask Change 22/Oct/2010 |
| 标准包装： | 750 |
| 类型： | 时钟/频率发生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，HSTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 750MHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
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AD9549
Rev. D | Page 62 of 76
Register 0x01AC to Register 0x01AD—Phase
Table 66.
Bits
Bit Name
Description
[7:0]
DDS phase word
Allows user to vary the phase of the DDS output. See the Direct Digital Synthesizer section. Register
0x01AC is the least significant byte of the phase offset word (POW). Note that a momentary phase
discontinuity may occur as the phase passes through 45° intervals. Active only when the loop is not closed.
Register 0x01AD—Phase (Continued)
Table 67.
Bits
Bit Name
Description
[15:8]
DDS phase word
Allows user to vary the phase of the DDS output. See the Direct Digital Synthesizer section. Register
0x01AC is the least significant byte of the phase offset word (POW). Note that a momentary phase
discontinuity may occur as the phase passes through 45° intervals. Active only when the loop is not closed.
REFERENCE SELECTOR/HOLDOVER (REGISTER 0x01C0 TO REGISTER 0x01C3)
Register 0x01C0—Automatic Control
Table 68.
Bits
Bit Name
Description
4
Holdover mode
This bit determines which frequency tuning word (FTW) is used in holdover mode.
0 = use last FTW at time of holdover.
1 = use averaged FTW at time of holdover, which is the recommended setting. The number of averages
used is set in Register 0x01C2.
3
Reserved
Reserved.
2
Automatic selector
Setting this bit permits state machine to switch the active reference clock input.
1
Automatic recover
Setting this bit permits state machine to leave holdover mode.
0
Automatic holdover
Setting this bit permits state machine to enter holdover (free-run) mode.
Register 0x01C1—Override
Table 69.
Bits
Bit Name
Description
4
Enable line card mode
Enables line card mode of reference switch MUX, which eliminates the possibility of a runt pulse during
switchover. See the Use of Line Card Mode to Eliminate Runt Pulses section.
3
Enable ref input
override
Setting this bit disables automatic reference switchover, and allows user to switch references manually
via Bit 2 of this register. Setting this bit overrides the REFSELECT pin.
2
REF_AB
This bit selects the input when Bit 3 of this register is set.
0 = REFA.
1
Enable holdover
override
Setting this bit disables automatic holdover and allows user to enter/exit holdover manually via Bit 0
(see the description for Bit 0). Setting this bit overrides the HOLDOVER pin.
0
Holdover on/off
This bit controls the status of holdover when Bit 1 of this register is set.
Register 0x01C2—Averaging Window
Table 70.
Bits
Bit Name
Description
[3:0]
FTW windowed
average size
This register sets the number of FTWs (frequency tuning words) that are used for calculating the average
FTW. Bit 4 in Register 0x01C0 enables this feature. An average size of at least 32,000 is recommended for
most applications. The number of averages equals 2(FTWWindowed Average Size [3:0]). These samples are taken at
the rate of (fs/2PIO).
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