- 您现在的位置：买卖IC网 > PDF目录1987 > AD9549ABCPZ-REEL7 (Analog Devices Inc)IC CLOCK GEN/SYNCHRONIZR 64LFCSP PDF资料下载
参数资料
| 型号： | AD9549ABCPZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 56/76页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 产品变化通告： | AD9549A Mask Change 22/Oct/2010 |
| 标准包装： | 750 |
| 类型： | 时钟/频率发生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太网，SONET/SDH，Stratum |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，HSTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 750MHz |
| 电源电压： | 1.71 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页当前第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页
AD9549
Rev. D | Page 6 of 76
AC SPECIFICATIONS
fS= 1 GHz, DAC RSET = 10 kΩ, power supply pins within the range specified in the DC Specifications section, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE INPUTS
Pin 12, Pin 13, Pin 15, and Pin 16
Frequency Range (Sine Wave)
10
750
MHz
Minimum recommended slew rate: 40 V/μs
Frequency Range (CMOS)
0.008
50
MHz
Frequency Range (LVPECL)
0.008
725
MHz
Frequency Range (LVDS)
0.008
725
MHz
LVDS must be ac-coupled; lower frequency bound may
be higher, depending on the size of the decoupling
capacitor
Minimum Slew Rate
0.04
V/ns
Minimum Pulse Width High
620
ps
Minimum Pulse Width Low
620
ps
FDBK_IN INPUT
Pin 40, Pin 41
Input Frequency Range
10
400
MHz
Minimum Differential Input Level
225
mV p-p
12 dBm into 50 ; must be ac-coupled
Minimum Slew Rate
40
V/μs
SYSTEM CLOCK INPUT
Pin 27, Pin 28
SYSCLK PLL Bypassed
Input Frequency Range
250
1000
MHz
Maximum fOUT is 0.4 × fSYSCLK
Duty Cycle
45
55
%
Minimum Differential Input Level
632
mV p-p
0 dBm into 50
SYSCLK PLL Enabled
VCO Frequency Range, Low Band
700
810
MHz
When in the range, use the low VCO band exclusively
VCO Frequency Range, Auto Band
810
900
MHz
When in the range, use the VCO Auto band select
VCO Frequency Range, High Band
900
1000
MHz
When in the range, use the high VCO band exclusively
Maximum Input Rate of System Clock PFD
200
MHz
Without SYSCLK PLL Doubler
Input Frequency Range
11
200
MHz
Multiplication Range
4
66
Integer multiples of 2, maximum PFD rate and system
clock frequency must be met
Minimum Differential Input Level
632
mV p-p
0 dBm into 50
With SYSCLK PLL Doubler
Input Frequency Range
6
100
MHz
Multiplication Range
8
132
Integer multiples of 8
Input Duty Cycle
50
%
Deviating from 50% duty cycle may adversely affect
spurious performance.
Minimum Differential Input Level
632
mV p-p
0 dBm into 50
Crystal Resonator with SYSCLK PLL Enabled
Crystal Resonator Frequency Range
10
50
MHz
AT cut, fundamental mode resonator
Maximum Crystal Motional Resistance
100
See the
SYSCLK Inputs section for recommendations
CLOCK DRIVERS
HSTL Output Driver
Frequency Range
20
725
MHz
See
Figure 12 for maximum toggle rate
Duty Cycle
48
52
%
Rise Time/Fall Time (20-80%)
115
165
ps
100 termination across OUT/OUTB, 2 pF load
Jitter (12 kHz to 20 MHz)
1.0
ps
fIN = 19.44 MHz, fOUT = 155.52 MHz. 50 MHz system
clock input (see
Figure 3 to Figure 11 for test conditions)
HSTL Output Driver with 2× Multiplier
Frequency Range
400
725
MHz
Duty Cycle
45
55
%
Rise Time/Fall Time (20% to 80%)
115
165
ps
100 termination across OUT/OUTB, 2 pF load
Subharmonic Spur Level
35
dBc
Without correction
Jitter (12 kHz to 20 MHz)
1.1
ps
fIN = 19.44 MHz, fOUT = 622.08 MHz, 50 MHz system
clock input (see
Figure 3 to Figure 11 for test conditions)
相关PDF资料 |
PDF描述 |
|---|---|
| AD9550BCPZ-REEL7 | IC INTEGER-N TRANSLATOR 32-LFCSP |
| AD9551BCPZ | IC CLOCK GEN MULTISERV 40-LFCSP |
| AD9552BCPZ-REEL7 | IC PLL CLOCK GEN LP 32LFCSP |
| AD9553BCPZ-REEL7 | IC INTEGER-N CLCK GEN 32LFCSP |
| AD9557BCPZ-REEL7 | IC CLK XLATR PLL 1250MHZ 40LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9549APCBZ | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549BCPZ | 制造商:Analog Devices 功能描述: |
| AD9549BCPZ-REEL7 | 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel |
| AD9549BCPZ-TR | 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel |
| AD9549XCPZ | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
发布紧急采购，3分钟左右您将得到回复。