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参数资料
型号： DS3105LN+
厂商： Maxim Integrated Products
文件页数： 13/124页
文件大小： 0K
描述： IC TIMING LINE CARD 64-LQFP
产品培训模块： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装： 160
类型： 定时卡 IC，多路复用器
PLL： 是
主要目的： 以太网，SONET/SDH，Stratum，电信
输入： CMOS，LVDS，LVPECL，TTL
输出： CMOS，LVDS，LVPECL，TTL
电路数： 1
比率 - 输入:输出： 5:2
差分 - 输入:输出： 无/是
频率 - 最大： 312.5MHz
电源电压： 1.62 V ~ 1.98 V
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 64-LQFP
供应商设备封装： 64-LQFP（10x10）
包装： 托盘
DS3105
11
5.
Detailed Features
5.1
Input Clock Features
Five input clocks: three CMOS/TTL (≤ 125MHz) and two LVDS/LVPECL/CMOS/TTL (≤ 156.25MHz)
CMOS/TTL input clocks accept any multiple of 2kHz up to 125MHz
LVDS/LVPECL inputs accept any multiple of 2kHz up to 131.072MHz, any multiple of 8kHz up to
155.52MHz plus 156.25MHz
All input clocks are constantly monitored by programmable activity monitors
Fast activity monitor can disqualify the selected reference after two missing clock cycles
Three optional 2/4/8kHz frame-sync inputs for frame-sync signals from master and slave timing cards and
an optional backup timing source
5.2
T0 DPLL Features
High-resolution DPLL plus three low-jitter output APLLs
Sophisticated state machine automatically transitions between free-run, locked, and holdover states
Revertive or nonrevertive reference selection algorithm
Programmable bandwidth from 18Hz to 400Hz
Separately configurable acquisition bandwidth and locked bandwidth
Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20
Multiple phase detectors: phase/frequency, early/late, and multicycle
Phase/frequency locking (
±360° capture) or nearest edge phase locking (±180° capture)
Multicycle phase detection and locking (up to
±8191UI) improves jitter tolerance and lock time
Phase build-out in response to reference switching
Less than 5ns output clock phase transient during phase build-out
Output phase adjustment up to
±200ns in 6ps steps with respect to selected input reference
High-resolution frequency and phase measurement
Holdover frequency averaging over 1 second interval
Fast detection of input clock failure and transition to holdover mode
Low-jitter frame sync (8kHz) and multiframe sync (2kHz) aligned with output clocks
5.3
T4 DPLL Features
High-resolution DPLL can be used to monitor inputs
Programmable bandwidth from 18Hz to 70Hz
Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20
Multiple phase detectors: phase/frequency, early/late, and multicycle
Phase/frequency locking (
±360° capture) or nearest edge phase locking (±180° capture)
Multicycle phase detection and locking (up to
±8191UI) improves jitter tolerance and lock time
Phase detector can be used to measure phase difference between two input clocks
High-resolution frequency and phase measurement
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