参数资料
型号: DS3105LN+
厂商: Maxim Integrated Products
文件页数: 33/124页
文件大小: 0K
描述: IC TIMING LINE CARD 64-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 160
类型: 定时卡 IC,多路复用器
PLL:
主要目的: 以太网,SONET/SDH,Stratum,电信
输入: CMOS,LVDS,LVPECL,TTL
输出: CMOS,LVDS,LVPECL,TTL
电路数: 1
比率 - 输入:输出: 5:2
差分 - 输入:输出: 无/是
频率 - 最大: 312.5MHz
电源电压: 1.62 V ~ 1.98 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
DS3105
16
Table 6-4. SPI Bus Mode Pin Descriptions
See Section 7.10 for functional description and Section 10.4 for timing specifications.
PIN NAME
PIN DESCRIPTION
CS
IPU
Chip Select. This pin must be asserted (low) to read or write internal registers.
SCLK
I
Serial Clock. SCLK is always driven by the SPI bus master.
SDI
I
Serial Data Input. The SPI bus master transmits data to the device on this pin.
SDO
O
Serial Data Output. The device transmits data to the SPI bus master on this pin.
CPHA
I
Clock Phase. See Figure 7-4.
0 = Data is latched on the leading edge of the SCLK pulse.
1 = Data is latched on the trailing edge of the SCLK pulse.
Table 6-5. JTAG Interface Pin Descriptions
See Section 9 for functional description and Section 10.5 for timing specifications.
PIN NAME
PIN DESCRIPTION
JTRST
IPU
JTAG Test Reset (Active Low). Asynchronously resets the test access port (TAP) controller. If
not used,
JTRST can be held low or high.
JTCLK
I
JTAG Clock. Shifts data into JTDI on the rising edge and out of JTDO on the falling edge. If
not used, JTCLK can be held low or high.
JTDI
IPU
JTAG Test Data Input. Test instructions and data are clocked in on this pin on the rising edge
of JTCLK. If not used, JTDI can be held low or high.
JTDO
O3
JTAG Test Data Output. Test instructions and data are clocked out on this pin on the falling
edge of JTCLK. If not used, leave unconnected.
JTMS
IPU
JTAG Test Mode Select. Sampled on the rising edge of JTCLK and is used to place the port
into the various defined IEEE 1149.1 states. If not used connect to VDDIO or leave
unconnected.
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