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参数资料
型号： DS3105LN+
厂商： Maxim Integrated Products
文件页数： 93/124页
文件大小： 0K
描述： IC TIMING LINE CARD 64-LQFP
产品培训模块： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装： 160
类型： 定时卡 IC，多路复用器
PLL： 是
主要目的： 以太网，SONET/SDH，Stratum，电信
输入： CMOS，LVDS，LVPECL，TTL
输出： CMOS，LVDS，LVPECL，TTL
电路数： 1
比率 - 输入:输出： 5:2
差分 - 输入:输出： 无/是
频率 - 最大： 312.5MHz
电源电压： 1.62 V ~ 1.98 V
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 64-LQFP
供应商设备封装： 64-LQFP（10x10）
包装： 托盘
DS3105
70
Register Name:
MCR3
Register Description:
Master Configuration Register 3
Register Address:
34h
Bit #
7
6
5
4
3
2
1
0
Name
AEFSEN
LKATO
XOEDGE
FRUNHO
EFSEN
SONSDH
—
REVERT
Default
1
0
1
see below
1
0
Bit 7: Auto External Frame-Sync Enable (AEFSEN). This bit has two functions depending on the external frame-
sync mode. See Section 7.9.1.
SYNC1 Modes:
0 = SYNC1 Manual mode: External frame sync is manually enabled on the SYNC1 pin when EFSEN = 1.
1 =SYNC1 Auto mode: External frame sync is automatically enabled on the SYNC1 pin when EFSEN = 1 and
the T0 DPLL is locked to the input clock specified in FSCR3:SOURCE.
SYNC123 Mode:
0 = EFSEN is not automatically cleared when the T0 DPLL’s selected reference changes.
1 = EFSEN is automatically cleared when the T0 DPLL’s selected reference changes.
(EFSEN must be set again by system software to enable it again.)
Bit 6: Phase-Lock Alarm Timeout (LKATO). This bit controls how phase alarms on input clocks can be
terminated. Phase alarms are indicated by the LOCK bits in ISR registers.
0 = Phase alarms on input clocks can only be cancelled by software.
1 = Phase alarms are automatically cancelled after a timeout period of 128 seconds.
Bit 5: Local Oscillator Edge (XOEDGE). This bit specifies the significant clock edge of the local oscillator clock
signal on the REFCLK input pin. The faster edge should be selected for best jitter performance. See Section 7.3.
0 = Rising edge
1 = Falling edge
Bit 4: Free-Run Holdover (FRUNHO). When this bit is set to 1 the T0 DPLL holdover frequency is set to 0ppm so
the output frequency accuracy is set by the external oscillator accuracy. This effects both mini-holdover and the
holdover state.
0 = Digital holdover
1 = Free-run holdover, 0ppm
Bit 3: External Frame-Sync Enable (EFSEN). When this bit is set to 1 the T0 DPLL looks for a frame-sync pulse
on the SYNCn pin(s). In SYNC123 mode, if AEFSEN = 1 EFSEN is automatically cleared when the T0 DPLL’s
selected reference changes. See Section 7.9.1.
0 = Disable external frame sync; ignore SYNCn pin(s)
1 = Enable external frame sync on SYNCn pin(s)
Bit 2: SONET or SDH Frequencies (SONSDH). This bit specifies the clock rate for input clocks with FREQ = 0001
in the ICR registers (20h to 28h). During reset the default value of this bit is latched from the SONSDH pin. See
Section 7.4.2.
0 = 2048kHz
1 = 1544kHz
Bit 0: Revertive Mode (REVERT). This bit configures the T0 DPLL for revertive or nonrevertive operation. (The T4
DPLL is always revertive). In revertive mode, if an input clock with a higher priority than the selected reference
becomes valid, the higher priority reference immediately becomes the selected reference. In nonrevertive mode the
higher priority reference does not immediately become the selected reference but does become the highest priority
reference in the priority table (REF1 field in the PTAB1 register). See Section 7.6.2.
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