参数资料
型号: DS3105LN+
厂商: Maxim Integrated Products
文件页数: 84/124页
文件大小: 0K
描述: IC TIMING LINE CARD 64-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 160
类型: 定时卡 IC,多路复用器
PLL:
主要目的: 以太网,SONET/SDH,Stratum,电信
输入: CMOS,LVDS,LVPECL,TTL
输出: CMOS,LVDS,LVPECL,TTL
电路数: 1
比率 - 输入:输出: 5:2
差分 - 输入:输出: 无/是
频率 - 最大: 312.5MHz
电源电压: 1.62 V ~ 1.98 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
DS3105
62
Register Name:
VALSR1
Register Description:
Input Clock Valid Status Register 1
Register Address:
0Eh
Bit #
7
6
5
4
3
2
1
0
Name
IC6
IC5
IC4
IC3
Default
0
Bits 5 to 2: Input Clock Valid Status (IC[6:3]). Each of these real-time status bits is set to 1 when the
corresponding input clock is valid. An input is valid if it has no active alarms (ACT = 0, LOCK = 0 in the
corresponding ISR register). See also the MSR1 register and Section 7.5.
0 = Invalid
1 = Valid
Register Name:
VALSR2
Register Description:
Input Clock Valid Status Register 2
Register Address:
0Fh
Bit #
7
6
5
4
3
2
1
0
Name
HORDY
IC9
Default
0
Bit 6: Holdover Frequency Ready (HORDY). This real-time status bit is set to 1 when the T0 DPLL has a
holdover value that has been averaged over the one-second holdover averaging period. See the related latched
status bit in MSR4 and Section 7.7.1.6.
Bit 0: Input Clock Valid Status (IC9). This bit has the same behavior as the bits in VALSR1 but for the IC9 clock.
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