参数资料
型号: EWIXP455ABT
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 266 MHz, RISC PROCESSOR, PBGA544
封装: LEAD FREE, PLASTIC, BGA-544
文件页数: 91/163页
文件大小: 1123K
代理商: EWIXP455ABT
Functional Overview
Intel IXP45X and Intel IXP46X Product Line of Network Processors Datasheet
May 2005
Document Number: 306261-002
33
3.2
Intel XScale Core
The Intel XScale technology is compliant with the Intel
StrongARM* Version 5TE instruction-set
architecture (ISA). The Intel XScale core, shown in Figure 4, is designed with Intel, 0.18-micron
production semiconductor process technology. This process technology — with the compactness of
the Intel
StrongARM* RISC ISA — enables the Intel XScale core to operate over a wide speed
and power range, producing industry-leading mW/MIPS performance.
Intel XScale core features include:
Seven/eight-stage super-pipeline promotes high-speed, efficient core performance
128-entry branch target buffer keeps pipeline filled with statistically correct branch choices
32-entry instruction memory-management unit for logical-to-physical address translation,
access permissions, and Instruction-Cache (I-cache) attributes
32-entry data-memory management unit for logical-to-physical address translation, access
permissions, Data-Cache (D-Cache) attributes
32-Kbyte instruction cache can hold entire programs, preventing core stalls caused by multi-
cycle memory accesses
32-Kbyte data cache reduces core stalls caused by multi-cycle memory accesses
2-Kbyte mini-data cache for frequently changing data streams avoids “thrashing” of the D-
cache
Four-entry, fill-and-pend buffers to promote core efficiency by allowing “hit-under-miss”
operation with data caches
Eight-entry write buffer allows the core to continue execution while data is written to memory
Multiple-accumulate coprocessor that can do two simultaneous, 16-bit, SIMD multiplies with
40-bit accumulation for efficient, high-quality media and signal processing
Performance monitoring unit (PMU) furnishing two 32-bit event counters and one 32-bit cycle
counter for analysis of hit rates, etc.
This PMU is for the Intel XScale core only. An additional PMU is supplied for monitoring of
internal bus performance.
JTAG debug unit that uses hardware break points and 256-entry trace history buffer (for flow-
change messages) to debug programs
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