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参数资料
| 型号： | FUSION878A |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 颜色信号转换 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封装： | PLASTIC, QFP-128 |
| 文件页数： | 147/180页 |
| 文件大小： | 2067K |
| 代理商： | FUSION878A |
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Fusion 878A
2.0 Functional Description
PCI Video Decoder
2.12 DMA Controller
100600B
Conexant
2-45
queued DWORDs. The DMA controller will ignore the FIFO trigger point
because it needs to empty the FIFO immediately. Otherwise it may not have a
chance to empty the rest of the FIFOs before it has to relinquish the bus. This is
not a concern in the packed mode because all three FIFOs are treated as one large
FIFO.
When the PCI target detects a parity error while the PCI initiator is reading the
instruction data, the DMA controller immediately stops burst data writes and
RISC instruction reads. This condition also causes an interrupt.
2.12.6 FIFO Overrun Conditions
There are cases where the Fusion 878A PCI initiator cannot gain control of the
PCI bus, and the DMA controller is not able to execute the necessary WRITE
instructions. Instead of writing data to the bus, the DMA controller reads data out
of the FIFO and discards the data. To the FIFO, it appears as if the DMA
controller is outputting to the bus. This allows the FIFO overruns to be handled
gracefully, with minimal loss of data. The Fusion 878A is not required to abort a
whole scan during FIFO overruns. The DMA controller keeps track of the data to
the nearest byte, and is able to deliver the rest of the scan line in case the FIFO
overrun condition is cleared.
The Fusion 878A DMA controller normally monitors the FIFO Full (FFULL)
counters to determine how full the FIFOs are. However, before the DMA
controller begins a burst write operation to process a WRITE instruction, it is
desirable to have some headroom in the FIFO allowing for more data to enter
while the PCI initiator is waiting for the target to respond. Hence, the Fusion
878A monitors the FIFO Almost Full (FAFULL) counters. The difference
between FFULL and FAFULL provides the necessary headroom to handle target
latency.
Before the DMA controller executes the address phase of a PCI write
transaction to process a WRITE instruction, the FIFO count value must be below
the FAFULL level. At all other times, the FIFOs must be maintained below the
FFULL level. The FIFO counters for all three FIFOs are monitored for full/almost
full conditions in both planar and packed modes.
Once the DMA controller begins the PCI bus transaction, it has committed to
a target DMA start address. If the FIFO overflows while it is waiting for the target
to respond, the initiator must terminate the transaction just after the target
responds. This is because the DMA controller has to start discarding the FIFO
data, since the target pointer and the data are out of sync. This terminating
condition will be communicated to the Fusion 878A device driver by setting an
interrupt bit that indicates interfacing to unreasonably slow targets (FBUS).
If an instruction is exhausted while the FIFO is in an overrun condition, the
Fusion 878A DMA controller will continue discarding the FIFO data during the
next pre-fetched instruction as well. If the DMA controller runs out of RISC
instructions and the FIFO continues to fill up, then PCI bus access is still denied.
The DMA controller continues discarding FIFO data for the remainder of that
scan line. Once the Fusion 878A DMA controller detects the EOL control bits
from the FIFO, it will attempt to gain access to the PCI bus and resynchronize
itself with the RISC instruction EOL status bits. However, if the DMA controller
is not successful in getting control of the bus, it will keep track of the number of
scan lines discarded out of the FIFO and will resynchronize itself with the RISC
program based on the number of EOL control signals detected.
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