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参数资料
| 型号： | FUSION878A |
| 厂商： | CONEXANT SYSTEMS |
| 元件分类： | 颜色信号转换 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封装： | PLASTIC, QFP-128 |
| 文件页数： | 9/180页 |
| 文件大小： | 2067K |
| 代理商： | FUSION878A |
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3.0 Electrical Interfaces
Fusion 878A
3.4 I2C Interface
PCI Video Decoder
3-22
Conexant
100600B
In the case where direct control of the I2C bus lines is desired, the Fusion
878A device driver can disable the I2C hardware control and can take software
control of the SCL and SDA pins. This is useful in applications where the I2C bus
is used for general purpose I/O or if a special type of I2C operation (such as
multi-mastering) needs to be implemented.
A transaction sequence involving a repeated START usually occurs after
setting up a slave read address using a 2-byte write transaction, then following
with a 1-byte read (with 1-byte slave address write) transaction. The STOP can be
disabled for the first transaction by setting I2CNOSTOP high only for the first
register write. I2CNOSTOP should be reset during the second register write
because every set of I2C transactions should begin with a START and end with a
STOP. (This rule is applicable to the overall transaction set or sequence).
Multi-byte (> 3) write transactions enable communication to devices that
support auto-increment internal addressing. To avoid reset of the internal address
sequencer in some devices, a STOP is not transmitted until the very end of the
sequence. The first register write should enable a 2-byte write transaction with
START. I2CNOSTOP should be set to disable STOPs temporarily. The SCL
signal will be held in the active low state while the I2CDONE interrupt is
processed. The second and successive register writes will enable 1-byte writes to
be transmitted without START and without STOP (I2CNOS1B, I2CNOSTOP
both high). The last register write should enable the final STOP to be sent to end
the sequential write transaction set. The 1-byte write data is sent from I2CDB0.
The R/W mode was saved from the first register write when the START was
transmitted.
For multi-byte (>1) sequential reads, the first register write enables the
START and slave address to be transmitted. The first read byte is received into
I2CDB2. The STOP is disabled via I2CNOSTOP. Since the reading continues, the
master should acknowledge at the end of the first read (set I2CW3BRA high).
The SCL signal will be held in the active low state while the I2CDONE interrupt
is processed.
The second and successive register writes will enable 1-byte reads to be
received without sending START or STOP (I2CNOS1B, I2CNOSTOP both high).
The last register write should reset I2CW3BRA low to master NACK. This will
indicate final read from slave, and enable the final STOP to be sent to end the
sequential read transaction set. The 1-byte read data is also read from I2CDB2.
The R/W mode was saved from the first register write when the START was
transmitted, so I2CDB0 is a Don’t Care during 1-byte reads.
For detailed information on the I2C bus, refer to The I2C-Bus Reference
Guide, reprinted by Conexant.
Figure 3-15. I2C Typical Protocol Diagram
DATAWRITE
DATAREAD
S
CHIP ADDR
A
SUB-ADDR
8 BITS
A
DATA
A
P
S
P
A
NA
= START
= STOP
= ACKNOWLEDGE
= NON ACKNOWLEDGE
S
CHIP ADDR
A
DATA NA
P
From Bt8xx to Slave
From Slave to Bt8xx
879A_046
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