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型号： HW-V5-ML561-UNI-G
厂商： Xilinx Inc
文件页数： 42/140页
文件大小： 0K
描述： EVALUATION PLATFORM VIRTEX-5
产品变化通告： Adapter Replacement 23/May/2008
Development Systems Discontinuation 16/Jan/2012
标准包装： 1
系列： Virtex®-5 LXT
类型： FPGA
适用于相关产品： XC5VLX50T-FFG1136
所含物品： 开发平台，小型闪存卡，缆线，DDR2 DIMM，电源和软件
相关产品： XC5VLX50T-3FFG665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-3FFG1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-3FF665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-3FF1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-2FFG665I-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-2FFG665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-2FFG1136I-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-2FFG1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-2FF665I-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-2FF665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA
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Chapter 4: Electrical Requirements
Table 4-2 lists the 12 different power planes on the Virtex-5 FPGA ML561 Development
Board. For the SSTL2, SSTL18, and HSTL power, separate power modules are
implemented for V CCO to FPGA, and V DD to memory, allowing for ease of power
measurement for the FPGAs. The power modules for V CCO inputs are implemented with
TI PTH05010 modules, which have provisions for ± 5% voltage margining pins.
R
Table 4-2:
Power Planes
Voltage Regulator Module (VRM) Part
TI PTH05010 15A Modules
TI PTH05000 6A Modules
Fairchild FN6555 3A Bus Term Regulators
(Separate outputs for V TT and V REF )
Power Plane
V CCINT Power Plane (1.0V)
SSTL18 FPGA Power Plane (1.8V)
HSTL FPGA Power Plane (1.8V)
V CCAUX Power Plane (2.5V)
SSTL2 FPGA Power Plane (2.6V)
TTL Power Plane (3.3V)
SSTL18 Memory Power Plane (1.8V)
HSTL Memory Power Plane (1.8V)
SSTL2 Memory Power Plane (2.6V)
SSTL18_VREF Power Plane (0.9V)
SSTL18_VTT Power Plane (0.9V)
HSTL_VREF Power Plane (0.9V)
HSTL_VTT Power Plane (0.9V)
SSTL2_VREF Power Plane (1.3V)
SSTL2_VTT Power Plane (1.3V)
VRM REFDES
VR6
VR1
VR10
VR12
VR9
VR13
VR4
VR14
VR2
U14
U42
U2
Stack-Up
Layer
Layer 4
Layer 7
Layer 8
Layer 11
Layer 8
Layer 11
Layer 7
Layer 8
Layer 8
Layer 8
Layer 8
Layer 7
Layer 7
Layer 7
Layer 7
Each of the three Fairchild FN6555 Bus Terminator Regulators has two voltage outputs:
one each for V REF and V TT . The FN6555 regulator is a push-pull device rated at ± 3A for the
V TT output and 3 mA for the V REF output.
Because the V REF voltage is used by the FPGA and memory devices only as reference, the
power supply does not source any real current. Thus the 3 mA capacity for the V REF output
is considered sufficient.
The V TT voltage is guaranteed to within ± 20 mV of the V REF output by the FN6555
regulator. The minimum driver output voltage swing around V REF is specified for the
SSTL18, SSTL2, and HSTL I/O standards as:
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?
?
SSTL2: ± 608 mV
SSTL18: ± 603 mV
HSTL: ± 500 mV (for HSTL18)
For a given memory interface, the maximum number of single-ended (non-differential)
signals that might need to be pulled up or down at a time for QDRII is 144 data bits and
approximately 30 address and control signals. The differential pair signals offset for the
sink and source of current. With a continuous current capacity of 3A for the FN6555
regulator, the regulator can supply up to (3000 / 175) = 17 mA of current per signal. The
maximum drive strength for a driver is specified at 16 mA. For a 50 Ω V TT termination, this
42
www.xilinx.com
Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
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