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参数资料
型号： HW-V5-ML561-UNI-G
厂商： Xilinx Inc
文件页数： 65/140页
文件大小： 0K
描述： EVALUATION PLATFORM VIRTEX-5
产品变化通告： Adapter Replacement 23/May/2008
Development Systems Discontinuation 16/Jan/2012
标准包装： 1
系列： Virtex®-5 LXT
类型： FPGA
适用于相关产品： XC5VLX50T-FFG1136
所含物品： 开发平台，小型闪存卡，缆线，DDR2 DIMM，电源和软件
相关产品： XC5VLX50T-3FFG665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-3FFG1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-3FF665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-3FF1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-2FFG665I-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-2FFG665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-2FFG1136I-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-2FFG1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-2FF665I-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-2FF665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA
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R
Signal Integrity Correlation Results
DDR2 Component Read Operation
This subsection shows the test results for the DDR2_DQ_BY2_B3 signal from the DDR2
memory component (U12) to FPGA1 (U7) measured at 333 MHz (667 Mb/s), where the
unit interval (UI) = 1.5 ns.
U12.D3
TL2
TL3
TL4
TL8
TL9
TL6
TL5
TL1
U7.P25
DQ3
28.5 ohms
MT47H64M8CB-3 3.579 ps
0.022 in
DDR2_DQ_BY2_B3
71.0 ohms
27.482 ps
AutoPadstk_3
DDR2_D…
22.9 fF
49.0 ohms
24.721 ps
0.164 in
DDR2_DQ_BY2_B3
DDR2_D… C9
22.9 fF 500.0 fF
58.3 ohms
25.244 ps
AutoPadstk_19
DDR2_D…
58.1 fF
49.1 ohms
47.132 ps
0.302 in
DDR2_DQ_BY2_B3
DDR2_D…
140.8 fF
49.1 ohms
445.560 ps
2.852 in
DDR2_DQ_BY2_B3
21.2 ohms
1.000 ps
AutoPadstk_3
DDR2_D…
C7
500.0 fF
365.6 fF
28.5 ohms
4.473 ps
0.028 in
DDR2_DQ_BY2_B3
DDR2_D…
22.9 fF
Virtex-5 FPGA
DDR2_DQ_BY2_B3
UG199_c7_12_071907
Figure 7-12:
Post-Layout IBIS Schematics of the DDR2 Component Read Data Bit (DDR2_DQ_BY2_B3)
Table 7-4:
Circuit Elements of DDR2 Component Read Data Bit
(DDR2_DQ_BY2_B3)
Element
Driver
Receiver
Probe Point
PCB Termination
Trace Length
Designation
U12.D3
U7.P25
C7
None
TL 2, 4, 9, 6, 1
Description
DDR2 Memory
FPGA SSTL18_II_DCI_I
Via under FPGA1
DCI at receiver
3.37 inches
Table 7-5:
DDR2 Component Read Operation Correlation Results
Measurement
Hardware at probe point
Simulation correlation
slow-weak corner
Correlation Delta:
HW vs. Simulation
Extrapolation at IOB
slow-weak corner
Extrapolation at IOB
fast-strong corner
DVW (% UI)
1.28 ns
(85%)
1.28 ns
(85%)
0 ps
(0.0%)
1.29 ns
(86%)
1.32 ns
(88%)
ISI
(% UI)
(70 + 110) = 180 ps
(12%)
(132 + 91) = 223 ps
(14.9%)
43 ps
(2.9%)
(96 + 82) = 178 ps
(11.9%)
(29 + 67) = 96 ps
(6.7%)
Noise Margin
(VIH + VIL) = Total
(% of VREF)
(423 + 416) = 839 mV
(83.1%)
(406 +439) = 845 mV
(83.8%)
6 mV
(0.7%)
(418 + 449) = 867 mV
(96.3%)
(455 +435) = 890 mV
(98.9%)
Overshoot /
Undershoot Margin
(% of VREF)
(400 +400) = 800 mV
(79.1%)
(279 +277) = 556 mV
(61.9%)
244 mV
(17.2%)
(304 +265) = 569 mV
(63.1%)
(167 +182) = 349 mV
(38.9%)
To perform hardware measurements for a Read operation that is not interrupted by a Write
or a Refresh operation, the testbench on FPGA1 is controlled by the following DIP switch
(SW2) setting:
?
DIP[1:2] = 2’b10 – Write once, then Read only, Refresh disabled
Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
www.xilinx.com
65
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