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型号： HW-V5-ML561-UNI-G
厂商： Xilinx Inc
文件页数： 76/140页
文件大小： 0K
描述： EVALUATION PLATFORM VIRTEX-5
产品变化通告： Adapter Replacement 23/May/2008
Development Systems Discontinuation 16/Jan/2012
标准包装： 1
系列： Virtex®-5 LXT
类型： FPGA
适用于相关产品： XC5VLX50T-FFG1136
所含物品： 开发平台，小型闪存卡，缆线，DDR2 DIMM，电源和软件
相关产品： XC5VLX50T-3FFG665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-3FFG1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-3FF665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-3FF1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-2FFG665I-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-2FFG665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-2FFG1136I-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-2FFG1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-2FF665I-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-2FF665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA
更多...
Chapter 7: ML561 Hardware-Simulation Correlation
DDR2 DIMM Read Operation
This subsection shows the test results for the DDR2_DIMM_DQ_BY2_B3 signal from the
DDR2 DIMM (XP2) to FPGA2 (U5) measured at 333 MHz (667 Mb/s), where the unit
interval (UI) = 1.5 ns.
R
49.8 ohms
49.8 ohms
49.8 ohms
49.8 ohms
49.1 ohms
49.1 ohms
28.5 ohms
94.605 ps
90.955 ps
90.340 ps
864.365 ps
59.1 ohms
78.216 ps
41.316 ps
71.6 ohms
4.473 ps
U3_B01.J1
59.8 ohms
3.590 ps
0.022 in
MDQ19_B01
59.8 ohms
31.503 ps
0.195 in
MDQ19_B01
59.8 ohms
78.962 ps
0.490 in
MDQ19_B01
RN6_B01
59.8 ohms
10.373 ps
0.064 in
DQ19_B01
J1_B01.31
0.606 in
DDR2_DIMM_DQ_...
TL15
0.582 in
DDR2_DIMM_DQ_...
TL16
0.578 in
DDR2_DIMM_DQ_...
TL17
5.533 in
DDR2_DIMM_DQ_...
TL18
12.486 ps 0.501 in
AutoPadstk_12_B... DDR2_DIMM_DQ_...
TL19 TL20
0.264 in 22.319 ps
DDR2_DIMM_DQ_... AutoPadstk_3_B00
TL7 TL6
0.028 in
DDR2_DIMM_DQ_...
TL3
U5_B00.H29
Virtex-5 FPGA
XP2_B00.31
XP3_B00.31
XP4_B00.31
XP5_B00.31
DIMM_DQ_BY2_B3
TL1
MT47H64M8CB_C...
DQ6
TL5
MDQ19_...
C13
TL11
22.0 ohms
TL12
????
TL14
????
50.3 ohms
23.650 ps
TL27
????
50.3 ohms
23.650 ps
TL23
????
50.3 ohms
23.650 ps
TL25
????
50.3 ohms
23.650 ps
DDR2_DI...
253.0 fF
DDR2_DI...
46.4 fF
DDR2_DI...
96.3 fF
C8
500.0 fF
DDR2_DI...
22.9 fF
17.3 fF
500.0 fF
DDR2_D...
R_00179...
0.0 milliohms
DDR2_D...
R7
0.0 milliohms
DDR2_D...
R5
0.0 milliohms
DDR2_D...
R6
0.0 milliohms
TL13
50.3 ohms
TL26
TL22
TL24
23.650 ps
DQ19_B...
50.3 ohms
23.650 ps
DQ19_B...
50.3 ohms
23.650 ps
DQ19_B...
50.3 ohms
23.650 ps
DQ19_B...
UG199_c7_30_071907
Figure 7-30:
Post-Layout IBIS Schematics of the DDR2 DIMM Read Data Bit (DDR2_DIMM_DQ_B)
Table 7-9:
Circuit Elements of DDR2 DIMM Read Data Bit
(DDR2_DIMM_DQ_BY2_B3)
Element
Driver
Receiver
Probe Point
PCB Termination
Trace Length
Designation
XP2-U3.J1
U5.H29
C8
None
Multiple TLs
Description
DDR2 DIMM
FPGA SSTL18_II_DCI_I
Via under FPGA2 (U5.H29)
DCI at load
8.975 inches
Table 7-10:
DDR2 DIMM Read Operation Correlation Results
Measurement
Hardware at probe
point
Simulation correlation
slow-weak corner
Correlation Delta:
HW vs. Simulation
Extrapolation at IOB
slow-weak corner
Extrapolation at IOB
fast-strong corner
DVW (%
UI)
904 ps
(60%)
865 ps
(59%)
39 ps
(2.6%)
1.23 ns
(82%)
1.24 ns
(83%)
ISI
(% UI)
(107 + 62) = 169 ps
(11.2%)
(130 + 83) = 213 ps
(14.2%)
44 ps (2.9%)
(139 + 75) = 224 ps
(14.9%)
(131 + 60) = 191 ps
(12.7%)
Noise Margin
(VIH + VIL) = Total
(% of VREF)
(242 + 258) = 500 mV
(+292 + 298) = 590 mV
90 mV (10%)
(243 + 303) = 546 mV
(60.7%)
(288 + 282) = 570 mV
(63.3%)
Overshoot / Undershoot
Margin
(% of VREF)
(623 + 613) = 1236 mV
(137.3%)
(524 + 504) = 1028 mV
(114.2%)
208 mV (23.1%)
(594 + 544) = 1138 mV
(116.5%)
(+481 + 508) = 989 mV
(109.9%)
To perform hardware measurements for a Read operation that is not interrupted by a Write
or a Refresh operation, the testbench on FPGA1 is controlled by the following DIP switch
(SW1) setting:
?
DIP[1:2] = 2’b10 – Write once, then Read only, Refresh disabled
76
www.xilinx.com
Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
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