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| 型号： | HW-V5-ML561-UNI-G |
| 厂商： | Xilinx Inc |
| 文件页数： | 91/140页 |
| 文件大小： | 0K |
| 描述： | EVALUATION PLATFORM VIRTEX-5 |
| 产品变化通告： | Adapter Replacement 23/May/2008 Development Systems Discontinuation 16/Jan/2012 |
| 标准包装： | 1 |
| 系列： | Virtex®-5 LXT |
| 类型： | FPGA |
| 适用于相关产品： | XC5VLX50T-FFG1136 |
| 所含物品： | 开发平台，小型闪存卡，缆线，DDR2 DIMM，电源和软件 |
| 相关产品： | XC5VLX50T-3FFG665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA XC5VLX50T-3FFG1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA XC5VLX50T-3FF665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA XC5VLX50T-3FF1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA XC5VLX50T-2FFG665I-ND - IC FPGA VIRTEX-5 50K 665FCBGA XC5VLX50T-2FFG665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA XC5VLX50T-2FFG1136I-ND - IC FPGA VIRTEX-5 50K 1136FBGA XC5VLX50T-2FFG1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA XC5VLX50T-2FF665I-ND - IC FPGA VIRTEX-5 50K 665FCBGA XC5VLX50T-2FF665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA 更多... |
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Summary and Recommendations
Summary and Recommendations
The first objective of this exercise is to establish correlation between hardware
measurements and the simulation at the probe point. The intention was to validate the
simulation model for the targeted signal. The degree of correlation achieved is looked at in
terms of absolute difference as well as relative percentage. The relative percentage
differences are presented in terms of unit interval (UI) for timing characteristics and in
terms of VREF voltage for the voltage margin characteristics.
Correlation simulation is performed under ideal conditions, that is, the stimulus is
generated without any jitter. On the other hand, the hardware measurements are subject to
jitter (which tends to increase ISI), board-level power fluctuation (which can affect the eye
amplitude), and stability of the probing station. Thus some correlation differences are
expected. The user ultimately uses his or her own judgment to account for these
differences, and adjusts the values extrapolated for quality of signal at the receiver IOB.
Table 7-15:
Summary of Correlation Differences: Hardware vs. Simulation
Operation
DDR2 Component Write
DDR2 Component Read
DDR2 DIMM Write
DDR2 DIMM Read
QDRII Write
QDRII Read
Δ DVW
(% UI (1) )
40 ps
(2.6%)
0 ps
(0%)
218 ps
(14.5%)
39 ps
(2.6%)
10 ps
(0.6%)
106 ps
(6.4%)
Δ ISI
(% UI)
47 ps
(3.2%)
43 ps
(2.9%)
366 ps
(24.5%)
44 ps
(2.9%)
107 ps
(6.4%)
27 ps
(1.6%)
Noise Margin
(% VREF)
98 mV
(10.9%)
6 mV
(0.7%)
112 mV
(12.6%)
90 mV
(10.0%)
2 mV
(0.3%)
386 mV
(31.8%)
Overshoot /
Undershoot Margin
(% VREF)
69 mV
(7.6%)
244 mV
(17.2%)
2 mV
(0.3%)
208 mV
(23.1%)
85 mV
(9.4%)
50 mV
(5.6%)
Notes:
1. Unit Interval (UI): 1.5 ns for DDR2 and 1.67 ns for QDRII. VREF = 0.9V for DDR2 and QDRII.
There are varying degrees of correlation differences among the six test signals. In general,
there is a good match between hardware measurements and the correlation simulation,
except for some yet-to-be analyzed differences, for example, DDR2 DIMM Write DVW and
QDRII read noise margin.
The remainder of this section summarizes the extrapolation results of the data bit interface
for all six memory operations on the ML561 board. The measure of SI characteristics of
each signal is determined by the worst-case extrapolation measurement from among the
simulations with drivers at slow-weak and fast-strong corners. The values chosen between
these two corner cases are:
?
?
Minimum of DVW, noise margin, and overshoot/undershoot margin
Maximum of ISI
Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
91
相关PDF资料 |
PDF描述 |
|---|---|
| I-JET | JTAG ARM DEBUGGING PROBE |
| IAC24A | INPUT MODULE AC 5MA 24VDC |
| IAC5EQ | INPUT MODULE AC 10MA 5VDC |
| IB8RM | SURGE SUPP 8OUT 12'CORD W/REMOTE |
| IBAR12-20T | SURGE SUPPRSSR 20A 12OUT RACKMNT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| HW-V5-ML561-UNI-G-J | 功能描述:EVALUATION PLATFORM VIRTEX-5 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Virtex®-5 LXT 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| HW-V5-PCIE2-UNI-G | 功能描述:KIT DEV PCIEXPRESS GTX VIRTEX5 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Virtex® -5 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
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