收藏本站
参数资料
型号： HW-V5-ML561-UNI-G
厂商： Xilinx Inc
文件页数： 47/140页
文件大小： 0K
描述： EVALUATION PLATFORM VIRTEX-5
产品变化通告： Adapter Replacement 23/May/2008
Development Systems Discontinuation 16/Jan/2012
标准包装： 1
系列： Virtex®-5 LXT
类型： FPGA
适用于相关产品： XC5VLX50T-FFG1136
所含物品： 开发平台，小型闪存卡，缆线，DDR2 DIMM，电源和软件
相关产品： XC5VLX50T-3FFG665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-3FFG1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-3FF665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-3FF1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-2FFG665I-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-2FFG665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-2FFG1136I-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-2FFG1136C-ND - IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-2FF665I-ND - IC FPGA VIRTEX-5 50K 665FCBGA
XC5VLX50T-2FF665C-ND - IC FPGA VIRTEX-5 50K 665FCBGA
更多...
R
Chapter 5
Signal Integrity Recommendations
Termination and Transmission Line Summaries
The following are common recommendations for the signal termination scheme to all
external memories implemented on the Virtex-5 FPGA ML561 Development Board:
?
?
?
Single-ended signals : Simulation indicates that for a single-ended signal, there is no
significant performance difference for a signal with split termination of 100 Ω + 100 Ω
between V DD and GND versus the V TT termination of 50 Ω to the V REF voltage.
Because the power consumption for the split termination is considerably higher than
the V TT termination for the SSTL2, SSTL18, and HSTL I/O standards, V TT termination
is recommended for single-ended signals on the board, such as data, address, and
control. For bidirectional single-ended signals (for example, DDR2 DQ), the V TT
termination is provided at both ends of the signal at the FPGA as well as at the
memory.
Differential signals : For differential pair signals, a 100 Ω differential termination is
provided between the two legs of the differential pair. This termination is placed
closest to the load. For bidirectional differential signals (for example, DDR2 DQS), the
differential SelectIO? primitives in Virtex-5 FPGAs (for example,
DIFF_SSTL_II_18_DCI), account for the differential termination within the IOB. So
external differential termination is required only at the memory.
Multiload signals : Address and control signals are driven by the FPGA, and they
have multiple loads. The termination is placed at the end of the trace after the last
load.
Table 5-1 through Table 5-5 summarize the specific termination schemes used on the
Virtex-5 FPGA ML561 Development Board for the following five different memory
interfaces. For each signal category, these tables include reference to the preliminary IBIS
simulation results (1) .
1.
2.
3.
4.
5.
DDR400 SDRAM Components ( Table 5-1 )
DDR2 SDRAM DIMM ( Table 5-2 )
DDR2 SDRAM Components ( Table 5-3 )
QDRII SRAM ( Table 5-4 )
RLDRAM II ( Table 5-5 )
1. Virtex-4 device IBIS models were used during the development of the ML561 board to understand the
expected signal integrity of the memory interface signals. When the Virtex-5 device IBIS models are available,
the results of post-layout IBIS simulations and characterization results will be reported.
Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
www.xilinx.com
47
相关PDF资料
PDF描述
I-JET JTAG ARM DEBUGGING PROBE
IAC24A INPUT MODULE AC 5MA 24VDC
IAC5EQ INPUT MODULE AC 10MA 5VDC
IB8RM SURGE SUPP 8OUT 12'CORD W/REMOTE
IBAR12-20T SURGE SUPPRSSR 20A 12OUT RACKMNT
相关代理商/技术参数
参数描述
HW-V5-ML561-UNI-G-J 功能描述:EVALUATION PLATFORM VIRTEX-5 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Virtex®-5 LXT 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
HW-V5-PCIE2-UNI-G 功能描述:KIT DEV PCIEXPRESS GTX VIRTEX5 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Virtex® -5 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
HW-VID-KIT 功能描述:可编程逻辑 IC 开发工具 Lattice Video Interface Kit RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压:
HW-VL1 制造商:IDEC CORPORATION 功能描述:BARRIER
HW-VL2 制造商:IDEC Corporation 功能描述:COVER;HW FNGR SAFE CONTAC CVR 制造商:IDEC CORPORATION 功能描述:HW FNGR SAFE CONTAC CVR
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*