参数资料
| 型号： | HW-XGI-VIDEO-US |
| 厂商： | Xilinx Inc |
| 文件页数： | 17/68页 |
| 文件大小： | 0K |
| 描述： | DAUGHTER CARD VIDEO I/O VIODC |
| 标准包装： | 1 |
| 其它名称： | 122-1506 HW-XGI-VIDEO-US-ND |
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Video Interface Support
SDI Video Interface – A complete SDI video interface capable of supporting both SD
and HD video rates is available on the VSK. The SDI standard is a high-speed serial
interface used to carry digital video over coax cable. It is generally used in a studio
environment. The SDI system includes cable equalizers and Genlock circuitry. (The
VSK is a demonstration platform only. For HD-SDI verification and compliance,
Xilinx recommends using the Cook Technologies SDV board ).
Clock Generator – The clock generator section is used to generate standard video
clock frequencies. It is based on an ICS 1523 clock generator IC.
XCV2P7 FPGA – The VSK also includes a Xilinx XCV2P7 FPGA, which is used to
interface to the various video interfaces, as well as the ML402 main board. It features
Multi-Gigabit Transceivers (MGTs), which are used to support the SDI interface. It
also enables the VIODC to be used in a stand-alone fashion.
XGI Connector – The XGI connector is a standard connector interface used on XiIinx
ML40 x FPGA development platforms. The XGI connector is used to connect to the
VIODC to a standard FPGA development platform, such as the ML402. The signals
consist of 32 single-ended LVCMOS25 signals and 32 signals that can be configured as
either 32 LVCMOS25 signals or 16 LVDS signal pairs. The LVDS pairs are length
matched and routed as pairs on the PCB. In addition, 5V power is passed up to the
VIODC over the XGI connector.
VIOBUS – The Video Starter Kit (VSK) uses the VIODC as a Video I/O interface. For
compatibility with the VSK, the 64 XGI signals have been specified as a bus named the
VIOBUS. In this use, the signals on the VIODC XGI connector have been specified as a
set of buses that transmit a 27-bit digital video channel from the VIODC to the FPGA
development platform and a 27-bit bus to transmit a similar digital video channel
from the ML40 x to the VIODC. Each video channel consists of a 24-bit digital video
bus, HSYNC, VSYNC and a clock enable signal. The pinout for the VIOBUS can be
found in Appendix A, “Reference Information.” This implementation of the interface
runs synchronous to the interface clock supplied by the ML402 board. The VIOBUS
also specifies an LVDS clock, a reset signal, an I2C interface, and a 4-pin serial bus.
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
17
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