参数资料
| 型号： | HW-XGI-VIDEO-US |
| 厂商： | Xilinx Inc |
| 文件页数： | 21/68页 |
| 文件大小： | 0K |
| 描述： | DAUGHTER CARD VIDEO I/O VIODC |
| 标准包装： | 1 |
| 其它名称： | 122-1506 HW-XGI-VIDEO-US-ND |
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R
Chapter 3
Component and S-Video Interfaces
Overview
The VIODC board supports input and output for S-video, composite, and component
video. Figure 3-1 is a simplified block diagram of input and output.
I2C
I2C
S-Video
Control
Control
S-Video
ADA4412
Composite
ADV7403
Video
Data
FPGA
Video
Data
ADV7321A
ADA4410
Composite
Component
ADA4412
Component
ug235_ch3_01_120805
Figure 3-1: S-Video, Composite, and Component Video Input and Output Block Diagram
Input signals are conditioned by a combination of passive components and the ADA4412
device. The conditioned input signals are converted to digital signals by the ADV7403
video decoder device. Digital video output data stream from the FPGA is converted to
analog signals by the ADV7321 video encoder device. The analog output signals are
conditioned by the ADA4410 device.
The video decoder, ADV7403 from Analog Devices, is responsible for converting analog
video signals into a representative digital video data stream. The video encoder,
ADV7321A also from Analog Devices, is responsible for the generation of S-Video,
composite, and component analog video signals from a digital video data stream. Both
devices offer an I 2 C control serial bus for control and ancillary data.
ADV7403 Video Decoder
The ADV7403 is a high quality, single chip, multiple format video decoder and graphics
digitizer. This multiple format decoder automatically supports the conversion of PAL,
NTSC, and SECAM standards in the form of composite or S-video into a digital ITU-R
BT.656 format. The component processor is capable of decoding/digitizing a wide
selection of video formats in any color space. Component video standards supported
include: 525i, 625i, 525p, 625p, 720p, 1080i and many other HD standards, as well as
graphic digitization from VGA to SXGA. Converted input signals are output to the output
pixel port, which is connected directly to the FPGA. Under user control, the output pixel
port is configurable to conform to multiple different standards. Selection of the format is
done through commands written to the device over the I 2 C bus and affects the pins
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
21
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