参数资料
| 型号： | HW-XGI-VIDEO-US |
| 厂商： | Xilinx Inc |
| 文件页数： | 27/68页 |
| 文件大小： | 0K |
| 描述： | DAUGHTER CARD VIDEO I/O VIODC |
| 标准包装： | 1 |
| 其它名称： | 122-1506 HW-XGI-VIDEO-US-ND |
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R
Component Video Input and Output
synchronization signals and field indicator. Figure 3-4 details the connections from the
ADV7403 video decoder device to the XC2VP4 Xilinx FPGA.
ADV7402 A
DP[41: 0]
VSYNC
HSYNC
FIELD
GENLOCK
LLC 1
42 DATA
VSYNC
HSYNC
FIELD
GENLOCK
LLC 1
XC2VP4
Clock Generation
ug235_ch3_06_121905
Figure 3-4: Connections from ADV7403 Video Decoder to XC2VP4 FGPA
Component Video Output
Compliant digital video streams are feed into the ADV7321 device by the Xilinx XC2VP4
FPGA, where it is converted to analog RGB or YPrPb using 12-bit DACs. The ADV7321
device, from Analog Devices, produces fully compliant SD/HD analog output signals,
which are then conditioned and drive the RCA type jacks. The Analog Devices ADV7321 is
used to generation all analog component RGB or YPrPb video output signals. Figure 3-5 is
a block diagram of the component video output system on the VIODC board.
Virtex-II Pro
XC2VP4
ADV7321
SD/HD Video
Encoder
Conditioning
Conditioning
Conditioning
RCA
RCA
RCA
RED
GRN
BLU
Analog
Component
Video
Output
Clock Generation
ug235_ch3_07_110805
Figure 3-5: Component Video Output Block Diagram
FPGA to ADV7321 Connection
The Xilinx XC2VP4 FPGA drives digital video data streams, in either standard and/or
high definition video format, onto three separate 10-bit wide digital input ports of the
ADV7321. For all supported standards the ADV7321 generates all horizontal, vertical and
blanking signals. Six high performance 12-bit digital to analog converters generate the
analog output signals.
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
27
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