参数资料
| 型号： | HW-XGI-VIDEO-US |
| 厂商： | Xilinx Inc |
| 文件页数： | 46/68页 |
| 文件大小： | 0K |
| 描述： | DAUGHTER CARD VIDEO I/O VIODC |
| 标准包装： | 1 |
| 其它名称： | 122-1506 HW-XGI-VIDEO-US-ND |
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Chapter 6: SDI Interface
R
The code running on the PicoBlaze processor also provides an interactive debugging
capability for viewing and changing the contents of the registers in the ADV7321B encoder.
A ChipScope? Pro VIO module is instantiated in the design to provide the user interface
to this debugging capability.
With the demo design loaded in the Virtex-II Pro FPGA on the VIODC, the debugger can
be activated by starting ChipScope Pro and loading the adv_debugger.cpj ChipScope
To read a register in the ADV7321B video encoder, simply type the register number in hex
in the Register Address field and click on the Read Strobe button. The data read from the
register is displayed in the Read Data field.
To write a register, type the register number in hex in the Register Address field and the
data to be written in hex in the Write Data field then click on the Write Strobe button. The
debugger will always do a read of the register after it is written and display the updated
value in the Read Data field.
Click here to reset the ADV7321B register
Enter register number of ADV7321B register to
be read or written here. Value is in hex.
Enter data to be written to ADV7321B register
here. Data is in hex.
Click here to write data to ADV7321B register.
Data read from ADV7321B register is
displayed here in hex.
Click here to read data from ADV7321B register.
ug235_ch6_02_111405
Figure 6-2:
ADV7321B Debugger
PAL mode.
Table 6-2: ADV7321B Register Settings for HD
Register Name
Power mode
Mode select
HD mode 2
HD mode 3
HD mode 4
Address
0x00
0x01
0x11
0x12
0x13
Value
0xFC
0x20
0x01
0x00
0x44
Description
Enable DACs
HD input only
Pixel data valid bit set to 1
Set all delays to 0
Set for 4:2:2 sampling and 10-bit data input
46
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
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