参数资料
| 型号： | HW-XGI-VIDEO-US |
| 厂商： | Xilinx Inc |
| 文件页数： | 19/68页 |
| 文件大小： | 0K |
| 描述： | DAUGHTER CARD VIDEO I/O VIODC |
| 标准包装： | 1 |
| 其它名称： | 122-1506 HW-XGI-VIDEO-US-ND |
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Chapter 2
VIODC to ML402 Card Interface
When the VIODC is used as part of the Video Starter Kit (VSK) from Xilinx, the 64-pin XGI
connector connects the VIODC to a ML402 card to communicate with the VIODC card.
When the VIODC is used with the VSK, the 64 XGI signals are allocated to a bus named the
VIOBUS, which serves the following functions:
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Transfers video data between the ML402 card and the VIODC card.
Provides a clock to the VIODC card.
Provides reset to the VIODC card.
Provides a low-pin count serial bus to access registers on the VIODC.
Provides an I2C bus (an industry standard 2-pin serial data bus used to communicate
and configure ICs ) to access registers on the VIODC video interface FPGA.
VIOBUS Clocking
The VIOBUS uses a simple synchronous interface running at 100 MHz ( Figure 2-1 ).
ML402 XC4VSX35
VIODC XC2VP7
100 MHz
Idelay
OBUF
CMOS25
CMOS25
LVDS
OBUF
IBUF +
Delay
Clock
BUFG
ug235_ch2_01_120805
Figure 2-1: VIOBUS Clocking
A clock is passed from the ML402 FPGA to the VIODC using differential signaling. All
data signals are single ended. The VIODC transmits data back to the ML402 FPGA using
the received clock. Data returning back from the VIODC is clocked into the ML402 FPGA
using the internal 100 MHz clock.
Future VIODC bus interfaces may implement a differential bus using the 16 differential
pairs available on HDR2 and more sophisticated clocking.
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
19
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