参数资料
| 型号： | HW-XGI-VIDEO-US |
| 厂商： | Xilinx Inc |
| 文件页数： | 26/68页 |
| 文件大小： | 0K |
| 描述： | DAUGHTER CARD VIDEO I/O VIODC |
| 标准包装： | 1 |
| 其它名称： | 122-1506 HW-XGI-VIDEO-US-ND |
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Chapter 3: Component and S-Video Interfaces
R
Component Video Input and Output
Component Video Input
RCA style connector J19 (X1, X3 and X5) enable input of analog component video signals,
which are then converted to the digital domain by the Analog Devices ADV7403 device.
Either YPrPb or RGB analog input signals are accepted. The ADV7403 devices integrated
110 MHz ADCs, with 12-bit resolution, supporting HDTV for 525p, 625p, 720p and 1080i as
well as RGB graphics support from VGA to SXGA at 60 frames per second. The digitized
video output is connected directly to the Xilinx FPGA through a digital data, video timing
control and I 2 C control busses. Figure 3-3 illustrates the VIODC composite video input
configuration, through ADV7403 video decoder to Xilinx XC2VP4 FPGA.
RED
RCA
Conditioning
ADV7403
GRN
RCA
Conditioning
SD/HD Video
Decoder
Virtex-II Pro
XC2VP4
RCA
Conditioning
BLU
Clock Generation
ug235_ch3_05_120805
Figure 3-3: Component Video Input
Input Signal Conditioning
The three RCA jacks X1, X3 and X5 are color coded Red, Green and Blue respectively and
form the physical connectors for the component video inputs. Conditioning of the analog
ADV7403 Connection to FPGA
Digital connections from the ADV7403 to the Xilinx XC2VP4 FPGA consist of 42 data and
5 control signals. The data signals include three 12-bit data busses for, one for each of red,
green and blue pixel values. Control signals include: horizontal and vertical frame
26
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
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