参数资料
| 型号： | HW-XGI-VIDEO-US |
| 厂商： | Xilinx Inc |
| 文件页数： | 36/68页 |
| 文件大小： | 0K |
| 描述： | DAUGHTER CARD VIDEO I/O VIODC |
| 标准包装： | 1 |
| 其它名称： | 122-1506 HW-XGI-VIDEO-US-ND |
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Chapter 4: DVI/VGA Input Interface
R
The HSYNC and VSYNC signals are critical to the VGA interface, but can be encoded in
several ways. The most basic is with separate sync signals for each, increasing the number
of signals to 5: RGBHV. These syncs can be active high or low, and different resolutions
typically have different combinations of sync polarity. A second encoding is composite HV,
with HSYNC and VSYNC combined onto a single signal. This is preformed through a
logical XOR of the two signals. The end result looks like the original HSYNC signal, except
that its polarity is inverted during VSYNC. This mode reduces the number of signals to 4.
A third mode of encoding the sync signals is by combining the composite sync signal with
the green data. This is referred to as “sync-on-green” (SOG). As mentioned previously, the
typical signal levels are 0-700mV. SOG offsets this by 300mV to 300mV-1V. The drop from
300mV to 0 is used to indicate the composite sync.
Table 4-1: VGA Standards
Pix
Clock
Freq
(MHz)
HSync
Freq
(kHz)
Front
Porch
Horizontal Timings
(in clk cycles)
Back
Sync
Porch
Active
Front
Porch
Vertical Timings
(in Lines)
Back
Sync
Porch
Active
VGA60
XGA60
SXGA60
UXGA60
40
65
108
162
37.9
48.4
64
75
40
24
48
64
128
136
112
192
88
160
248
304
800
1024
1280
1600
1
3
1
1
4
6
3
3
23
29
38
46
600
768
1024
1200
Setting the PLL and Phase
The AD9887A digitizes the analog video waveforms using three 8-bit analog-to-digital
converters. For this analog-to-digital conversion to operate properly, it must sample each
pixel at the appropriate time ( Figure 4-4 ).
1 1
2
12 Active Pixels
1 1
2
RGB
10
11
0
1
2
3
4
5
6
7
8
9
10
11
0
HSYNC
Figure 4-4: Pixel Sampling
To explain VGA sampling theory, it is useful to use a greatly simplified example. Figure 4-4
shows a single line from a frame with the horizontal front porch set to 1, the sync length set
to 1, and the horizontal back porch set to 2. The line has 12 active pixels. In order to receive
the video data, these are the only signals available.
sample times, the AD9887A includes a PLL that locks to the incoming HSYNC,
multiplying the HSYNC frequency by a factor set by the feedback divider. The frequency
multiplication factor is set to the total number of clock cycles per HSYNC period. For the
free-running, so ADC samples occur during blanking (gray arrows) as well as active video
36
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
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