参数资料
| 型号： | HW-XGI-VIDEO-US |
| 厂商： | Xilinx Inc |
| 文件页数： | 34/68页 |
| 文件大小： | 0K |
| 描述： | DAUGHTER CARD VIDEO I/O VIODC |
| 标准包装： | 1 |
| 其它名称： | 122-1506 HW-XGI-VIDEO-US-ND |
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Chapter 4: DVI/VGA Input Interface
R
DVI Interface
The DVI interface is through the DVI-I connector. The video data is carried by four
differential pairs, three data and a clock.
VGA interface
The analog VGA interface is through the either the HD15 connector or the analog pins of
the DVI-I connector. The video data is carried by three analog signals along with up to two
optional sync signals.
Display Data Channel
Both the DVI connector and the HD15 connector include SCL and SDA pins for the Display
Data Channel (DDC). This is an I2C interface used by a computer to identify a monitor ’s
capabilities. The graphics adapter reads the monitor ’s extended display identification data
(EDID). This structure lists monitor manufacturer and model, supported resolutions, and
other capabilities. If a graphics adapter cannot retrieve this EDID structure, it runs with a
default resolution, typically 640 x 480 at 60 Hz analog. To allow higher resolutions or to
enable the DVI interface, the receiver must report that it is capable of these modes. To
support this, VIODC includes EEPROMs on the DDC (separate for each connector) that
can be programmed with this structure.
The DDC is also used in the DVI connector for negotiating encryption keys when High-
bandwidth Digital Content Protection (HDCP) is required. The AD9887A interface
supports this functionality and has an EEPROM for storing these keys.
AD9887 Overview
The AD9887A dual interface includes both analog and digital interfaces. Refer to the
AD9887A interface data sheet for further details.
Analog Interface
The AD9887A is a complete 8-bit 170 mega sample per second (MSPS) monolithic analog
interface optimized for capturing RGB graphics signals from personal computers and
workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of
330 MHz supports resolutions up to UXGA (1600 by 1200 at 60 Hz).
The analog interface includes a 170 MHz triple ADC with internal 1.25 V reference, a
phase-locked loop (PLL), and programmable gain, offset, and clamp control. The user
provides only a 3.3 V power supply, analog input, and HSYNC. Three-state CMOS outputs
can be powered from 2.5 V to 3.3 V.
The AD9887A’s on-chip PLL generates a pixel clock from HSYNC. Pixel clock output
frequencies range from 12 MHz to 170 MHz. PLL clock jitter is typically 500 ps peak-to-
peak at 170 MSPS. The AD9887A also offers full sync processing for composite sync and
sync-on-green (SOG) applications.
Digital Interface
The AD9887A contains a DVI 1.0 compatible receiver and supports display resolutions up
to UXGA (1600 _ 1200 at 60 Hz). The receiver operates with true color (24-bit) panels in 1 or
34
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
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