参数资料
型号: HW-XGI-VIDEO-US
厂商: Xilinx Inc
文件页数: 35/68页
文件大小: 0K
描述: DAUGHTER CARD VIDEO I/O VIODC
标准包装: 1
其它名称: 122-1506
HW-XGI-VIDEO-US-ND
R
VGA Standard Overview
2 pixel(s)/clock mode and features an intra-pair skew tolerance of up to one full clock
cycle.
With the inclusion of HDCP, displays can now receive encrypted video content. The
AD9887A allows for authentication of a video receiver, decryption of encoded data at the
receiver, and renewability of that authentication during transmission as specified by the
HDCP v1.0 protocol.
VGA Standard Overview
The dominant video monitor interface standard for PCs has been analog VGA since its
establishment in 1987. The VGA interface consists of RGB pixel levels and synchronization
signaling (syncs). This interface was designed specifically for driving CRT monitors, so
this interface is tailored to work with CRTs.
The video data is carried by three 75 Ω transmission lines (coax), one each for red, green,
and blue. When 75 Ω terminated at the monitor, the voltage typically ranges from
0 mV - 700 mV. This voltage indicates 0% - 100% intensity on the associated color. In a CRT,
these voltages adjust the intensity of the electron beam for each color.
Figure 4-2: VGA Interface
Synchronization signaling is used to control the scanning of the electron beams, giving the
stream of RGB video data positional significance. This signaling is a combination of two
timing signals: horizontal synchronization and vertical synchronization (HSYNC and
VSYNC). HSYNC resets the beam to the left edge of the screen, and when released it
sweeps to the right. VSYNC resets the beam to the top of the screen, and when released it
slowly sweeps downward. The monitor locks its vertical and horizontal sweep rates to the
VSYNC and HSYNC frequencies, respectively.
RGB
HSYNC
VSYNC
RGB
Video Data
HSYNC
Figure 4-3: Synchronization Signaling
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
35
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