参数资料
| 型号： | HW-XGI-VIDEO-US |
| 厂商： | Xilinx Inc |
| 文件页数： | 43/68页 |
| 文件大小： | 0K |
| 描述： | DAUGHTER CARD VIDEO I/O VIODC |
| 标准包装： | 1 |
| 其它名称： | 122-1506 HW-XGI-VIDEO-US-ND |
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Chapter 6
SDI Interface
Introduction
This chapter describes how the demo is implemented. More detailed descriptions of how
to implement SD-SDI and HD-SDI transmitters and receivers can be found in Xilinx
application notes, XAPP683 , XAPP684 , XAPP579 , and various other SDI-related Xilinx
application notes. (The VSK is a demonstration platform only. For HD-SDI verification and
compliance, Xilinx recommends using the Cook Technologies SDV board ).
This chapter demonstrates the use of the SDI interfaces on the VIODC in both SD-SDI and
HD-SDI modes and provides a basic demonstration of how to implement the SDI receiver
and transmitter interface. The code provided can easily be modified to send the video
received by the SDI receiver to different video interfaces or to the ML402 board for further
processing. Likewise, the code can be modified so that the video source for the SDI
transmitter comes from other video sources other than the internal video pattern
generators.
The chapter also demonstrates how to use the ADV7321B video encoder device to convert
digital video received by the SDI receiver into analog video. A PicoBlaze? processor is
used to control the ADV7321B video encoder through the I2C interface. The PicoBlaze
processor code includes an interactive debugger allowing registers in the ADV7321B to be
read or written through a ChipScope? video input and output (VIO) console.
Reference Clocks
The source of reference clocks for the SDI transmitter and receiver is a combination of a
voltage controlled crystal oscillator (VCXO) (PLL502) and a frequency synthesizer
(ICS664-02).
The PLL502 VCXO is based on a 13.5 MHz crystal. The VCXO can multiply this crystal
frequency by various multipliers. The control voltage for the VCXO comes from a Digital-
to-Analog Converter (DAC). The DAC is controlled by the FPGA. In this demo, the DAC
outputs a fixed voltage at about the 1.65 V.
The output of the VCXO is connected to the clock input of the ICS664-02 frequency
synthesizer. The ICS664-02 can generate various different frequencies from the reference
clock frequency supplied by the VCXO.
The RocketIO? transceiver used in the SDI receiver needs three different clock
frequencies: 74.25 MHz (to receive 1.485 Gb/s HD-SDI), 74.1758 MHz (to receive
1.4835 Gb/s HD-SDI), and 108 MHz (to receive 270 Mb/s SD-SDI). In the transmitter
section, the RocketIO transceiver also needs three clock frequencies: 74.25 MHz,
74.1758 MHz, and 54 MHz. (1)
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
43
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