参数资料
型号: HW-XGI-VIDEO-US
厂商: Xilinx Inc
文件页数: 20/68页
文件大小: 0K
描述: DAUGHTER CARD VIDEO I/O VIODC
标准包装: 1
其它名称: 122-1506
HW-XGI-VIDEO-US-ND
Chapter 2: VIODC to ML402 Card Interface
VIOBUS Signal Definitions
Table 2-1: VIOBUS Signal Definitions
R
Signal
Description
nbits
Type
Target
Speed
Source
FPGA
XGI Pins
VIO Data Bus (a moderate-speed single-ended bus)
vio_up[25:0]
Data bus to the VIODC
26
LVCMOS25
100 MHz
ML402
hdr1[20:2],
hdr2[2:32]
vio_up_ena
Pixel enable for
1
LVCMOS25
100 Mhz
ML402
hdr1[22]
vio_up[25:0]
vio_dn[25:0]
Data bus from the VIODC
26
LVCMOS25
100 MHz
VIODC
hdr1[42:24],
hdr2[64:34]
vio_dn_ena
Pixel enable for
1
LVCMOS25
100 MHz
VIODC
hdr1[44]
vio_up[25:0]
Sport Serial Bus (used to configure registers in the VIODC FPGA)
vio_sport_up
Sport write data (16-bit
1
LVCMOS25
10 MHz
ML402
hdr1[54]
data, 16-bit address)
vio_sport_dn
vio_sport_sync
vio_sport_clk
Sport return data
Sport sync pulse
Sport clock
1
1
1
LVCMOS25
LVCMOS25
LVCMOS25
10 MHz
10 MHz
10 MHz
VIODC
ML402
ML402
hdr1[52]
hdr1[50]
hdr1[48]
I2C Serial Bus (used to configure registers in the video devices)
vio_i2c_sda_up
vio_i2c_sda_dn
vio_i2c_scl_up
I2C write data
I2C return data
I2C clock signal
1
1
1
LVCMOS25
LVCMOS25
LVCMOS25
400 kHz
400 kHz
400 kHz
ML402
VIODC
ML402
hdr1[60]
hdr1[58]
hdr1[56]
Miscellaneous
vio_reset
Active High reset to
1
LVCMOS25
10 MHz
ML402
hdr1[46]
VIODC
Clock
vio_up_clk_lvds_P,N
1
LVDS25
400 MHz
ML402
hdr1[64:62]]
Refer to the VIOBUS pinout in Appendix A, “Reference Information” for signal locations.
20
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
相关PDF资料
PDF描述
ICD15S13E6GV00LF CONN DSUB HD SOCKT 15POS R/A PCB
ICD26S13E4GX00LF CONN DSUB HD SOCKT 26POS R/A PCB
ID09S33E4GV00LF CONN RCPT 9POS R/A GOLD
ID451000 CONN RECPT USB A ADAPTER
IELHK11-1-72-70.0-01-V CIRCUIT BREAKER HYMAG DP 70A
相关代理商/技术参数
参数描述
HWXX35338TR 制造商:Vishay Intertechnologies 功能描述:
HWXX38438 制造商:Vishay Semiconductors 功能描述:
HWZ1408 制造商:OHIO BUCKEYE 功能描述:
HWZ1424 制造商:OHIO BUCKEYE 功能描述:
HWZ1620 制造商:OHIO BUCKEYE 功能描述: