参数资料
| 型号： | HW-XGI-VIDEO-US |
| 厂商： | Xilinx Inc |
| 文件页数： | 44/68页 |
| 文件大小： | 0K |
| 描述： | DAUGHTER CARD VIDEO I/O VIODC |
| 标准包装： | 1 |
| 其它名称： | 122-1506 HW-XGI-VIDEO-US-ND |
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Chapter 6: SDI Interface
configured for the three different SDI bit rates. In SD-SDI mode, the 54 MHz clock out of
the ICS664-02 is multiplied by two by a Digital Clock Manager (DCM) to produce the
108 MHz reference clock needed by the RocketIO transceiver in the SDI receiver.
Table 6-1: RocketIO Reference Clock Generation
R
Bit Rate
1.485 Gb/s
1.4835 Gb/s
270 Mb/s
VCXO
Frequency
13.5 MHz
13.5 MHz
54 MHz
ICS664-02 Frequency
74.25 MHz
74.1758 MHz
54 MHz
Rx REFCLK
74.25 MHz
74.1758 MHz
108 MHz
Tx REFCLK
74.25 MHz
74.1758 MHz
54 MHz
SDI Receiver
the FPGA.
The serial bitstream enters the RocketIO receiver after passing through an SDI cable
equalizer. The RocketIO receiver must be give a reference clock of the appropriate
frequency depending on the bit rate being received. If the reference clock frequency
doesn’t match the bit rate of the input bitstream the receiver will not lock to the bitstream.
If the demo is in Auto Rx mode, the automatic rate detection logic will sequence the
RocketIO receiver through the three different bit rates supported by the demo until the
receiver locks.
27 MHz Clock Enable
SD-SDI
Data
Recovery
10
SD-SDI
Descrambler
10
SD-SDI
Framer
10
EDH
Checker
10
S
SD
Analog
SDI In
Cable
RXP
clk
Video
Equalizer
DCM
108 MHz
RXN
RocketIO
RXDATA
REFCLK2
20
HD-SDI
Descrambler
20
10
HD-SDI Y
Framer C 10
hd_sd
Y
C
HD
Analog
Video
hd_sd
74.25 MHz or
74.1758 MHz
ICS664-02
REFCLKSEL
REFCLK RXRECCLK
RXUSRCLK
RXUSRCLK2
BUFG
AutoRate
Detection
CRC Check
freq control
From ML402
DIP switches
Demo Mode
Control
hd_sd
freq control
ug235_ch5_01_111405
Figure 6-1: SDI Receiver Block Diagram
1. It is possible to use 108 MHz instead of 54 MHz for SD-SDI in the transmitter. However, because the ICS664-
02 cannot directly generate 108 MHz, a DCM would be required to generate the 108 MHz clock resulting in
more jitter on the output of the SDI transmitter due to higher jitter on the reference clock. The receiver section
requires 108 MHz and cannot get by with 54 MHz. However, jitter on the RocketIO reference clock is not as
important for the receiver.
44
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
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