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| 型号： | M68HC705UGANG |
| 厂商： | 飞思卡尔半导体(中国)有限公司 |
| 英文描述： | High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit |
| 中文描述： | 高密度互补金属氧化物半导体（HCMOS）微控制器 |
| 文件页数： | 23/112页 |
| 文件大小： | 809K |
| 代理商： | M68HC705UGANG |
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MC68HC05BD3
2-3
PIN DESCRIPTION AND I/O PORTS
2
2.3
INPUT/OUTPUT PORTS
In the User Mode there are 24 bidirectional I/O lines arranged as 4 I/O ports (Port A, B, C, and D).
The individual bits in these ports are programmable as either inputs or outputs under software
control by the data direction registers (DDRs). Also, if enabled by software, Port C and D will have
additional functions as PWM outputs, M-Bus I/O and Sync Signal Processor outputs.
2.3.1
Port A
Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems.
The Port A data register is at $00 and the data direction register (DDR) is at $04. Reset does not
affect the data register, yet clears the data direction register, thereby returning the ports to inputs.
Writing a one to a DDR bit sets the corresponding port bit to output mode.
2.3.2
Port B
Port B is a 6-bit bidirectional port which does not share any of its pins with other subsystems. PB2
to PB5 are +10V open-drain port pins. The Port B data register is at $01 and the data direction
register (DDR) is at $05. Reset does not affect the data register, yet clears the data direction
register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding
port bit to output mode.
Figure 2-2
Pin Assignment for 42-pin SDIP Package
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
PWM2
PWM1
PWM0
RESET
VDD
NC
VSS
XTAL
EXTAL
PB5
PB4
PB3
PB2
PB1
PB0
IRQ/VPP
PA7
PA6
PA5
PA4
PA3
VSYNC
HSYNC
PWM3
PWM4
PWM5
NC
PWM6
PWM7
PC7/PWM15/HTTL
PC6/PWM14/VTTL
PC5/PWM13
PC4/PWM12
PC3/PWM11
PC2/PWM10
PC1/PWM9
PC0/PWM8
PD1/SCL
PD0/SDA
PA0
PA1
PA2
TPG
21
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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