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| 型号： | M68HC705UGANG |
| 厂商： | 飞思卡尔半导体(中国)有限公司 |
| 英文描述： | High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit |
| 中文描述： | 高密度互补金属氧化物半导体（HCMOS）微控制器 |
| 文件页数： | 59/112页 |
| 文件大小： | 809K |
| 代理商： | M68HC705UGANG |
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MC68HC05BD3
7-13
M-BUS SERIAL INTERFACE
7
LAMAR
BSET
3,MCR
; LAST SECOND, DISABLE ACK
; TRANSMITTING
BRA
NXMAR
5,MCR
ENMASR BCLR
; LAST ONE, GENERATE 'STOP'
; SIGNAL
; READ DATA AND STORE
NXMAR
LDA
STA
RTI
MDR
RXBUF
7.4.5
Generation of a Repeated START Signal
At the end of data transfer, if the master still wants to communicate on the bus, it can generate
another START signal followed by another slave address without first generating a STOP signal.
A program example is as shown.
RESTART
BCLR
BSET
5,MCR
5,MCR
; ANOTHER START (RESTART) IS
; GENERATED BY THESE TWO
; CONSECUTIVE INSTRUCTIONS
; GET THE CALLING ADDRESS
; TRANSMIT THE CALLING
; ADDRESS
LDA
STA
#CALLING
MDR
7.4.6
Slave Mode
In the slave service routine, the master addressed as slave bit (MAAS) should be tested to check
if a calling of its own address has been received (Figure 7-4). If MAAS is set, software should set
the transmit/receive mode select bit (MTX bit of MCR) according to the R/W command bit (SRW).
Writing to the MCR clears the MAAS automatically. A data transfer may then be initiated by writing
to MDR or a dummy read from MDR.
In the slave transmit routine, the received acknowledge bit (RXAK) must be tested before
transmitting the next byte of data. RXAK, if set indicates the end of data signal from the master
receiver, the slave transmitter must then switch from transmit mode to receive mode by software
and a dummy read must follow to release the SCL line so that the master can generate a STOP
signal.
7.4.7
Arbitration Lost
If more than one master want to acquire the bus simultaneously, only one master can win and the
others will lose arbitration. The losing device immediately switches to slave receive mode by
M-Bus hardware. Its data output to the SDA line is stopped, but internal transmit clock still runs
until the end of the data byte transmission. An interrupt occurs when this dummy byte transmission
TPG
57
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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