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| 型号： | M68HC705UGANG |
| 厂商： | 飞思卡尔半导体(中国)有限公司 |
| 英文描述： | High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit |
| 中文描述： | 高密度互补金属氧化物半导体（HCMOS）微控制器 |
| 文件页数： | 70/112页 |
| 文件大小： | 809K |
| 代理商： | M68HC705UGANG |
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8-10
MC68HC05BD3
SYNC SIGNAL PROCESSOR
8
sync input. The data can be read to determine if the line frequency is valid and to determine the
video mode. However, the data is not valid if HDET or VDET bit is cleared or HOVER bit is set.
User has to determine whether the incoming signal is separate sync or composite sync. If
composite sync signal is input, the actual number of horizontal lines is the value in LFR plus one;
because the internal line counter that counts the horizontal sync pulses is rising-edge triggering.
If the incoming signal is a composite signal, one horizontal line counting is missed.
8.3.4
Sync Signal Control Register (SSCR)
This is a read/write register. Interrupt will be generated at the leading edge of VSYNC if the VSIE
bit is set, I bit in CCR is cleared. The VSYNC interrupt vectors are at $3FF8 and $3FF9, and the
interrupt latch is cleared after the interrupt vectors have been fetched.
VSIE - Vsync Interrupt Enable
This bit enables and disables the Vsync interrupt.
1 (set)
–
Vsync interrupt enabled.
0 (clear) –
Vsync interrupt disabled.
8.3.5
Horizontal Sync Period Width Register (HPWR)
This 8-bit read only register contains the period of incoming horizontal sync signal. It is sampled
by t
CYC
so the horizontal period is equal to HPWR x 0.5
μ
s if t
CYC
is at 2MHz. As the incoming
horizontal sync signal is asynchronous to the system clock, the SSP is designed so that the
maximum counting error of HPWR is –2. User should use the LFR to calculate the HSYNC
frequency if very accurate frequency detection is needed. If HPWR overflows, the HDET in
SSCSR will be cleared. Therefore the minimum valid HSYNC is 256t
CYC
, i.e. 7.8125KHz if t
CYC
equals to 2MHz.
Note:
It is not guaranteed that the HPWR counting is correct for the first HSYNC period after
the trailing edge of VSYNC.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0011
VSIE
0000 0000
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$001E
HPWR7
HPWR6
HPWR5
HPWR4
HPWR3
HPWR2
HPWR1
HPWR0
0000 0000
TPG
68
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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