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| 型号： | M68HC705UGANG |
| 厂商： | 飞思卡尔半导体(中国)有限公司 |
| 英文描述： | High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit |
| 中文描述： | 高密度互补金属氧化物半导体（HCMOS）微控制器 |
| 文件页数： | 24/112页 |
| 文件大小： | 809K |
| 代理商： | M68HC705UGANG |
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2-4
MC68HC05BD3
PIN DESCRIPTION AND I/O PORTS
2
2.3.3
Port C
Port C is an 8-bit bidirectional port which shares pins with PWM and SSP subsystem. See
Section 6 for a detailed description of PWM and Section 8 for a detailed description of SSP. These
pins are configured to PWM output when the corresponding bits in the Configuration register 1 are
set, except PC6 and PC7. PC6 and PC7 are configured to SSP outputs when the corresponding
bits in the Configuration register 2 are set. The Port C data register is at $02 and the data direction
register (DDR) is at $06. Reset does not affect the data register, but clears the data direction
register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding
port bit to output mode.
2.3.4
Port D
Port D is a 2-bit bidirectional port which shares pins with M-Bus subsystem. See Section 7 for a
detailed description of M-Bus. These pins are configured to the corresponding functions when the
corresponding bits in the Configuration register 2 are set. They are +5V open-drain I/O pins when
used as M-Bus I/O. The Port D data register is at $03 and the data direction register (DDR) is at
$07. Reset does not affect the data register, yet clears the data direction register, thereby returning
the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode.
2.3.5
Input/Output Programming
Bidirectional port lines may be programmed as an input or an output under software control. The
direction of the pins is determined by the state of the corresponding bit in the port data direction
register (DDR). Each port has an associated DDR. Any I/O port pin is configured as an output if
its corresponding DDR bit is set. A pin is configured as an input if its corresponding DDR bit is
cleared.
During Reset, all DDRs are cleared, which configure all port pins as inputs. The data direction
registers are capable of being written to or read by the processor. During the programmed output
state, a read of the data register actually reads the value of the output data latch and not the I/O
pin.
Table 2-1
I/O Pin Functions
R/W
0
0
1
1
DDR
0
1
0
1
I/O Pin Function
The I/O pin is in input mode. Data is written into the output data latch.
Data is written into the output data latch and output to the I/O pin.
The state of the I/O pin is read.
The I/O pin is in an output mode. The output data latch is read.
TPG
22
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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