参数资料
型号: M68HC705UGANG
厂商: 飞思卡尔半导体(中国)有限公司
英文描述: High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
中文描述: 高密度互补金属氧化物半导体(HCMOS)微控制器
文件页数: 63/112页
文件大小: 809K
代理商: M68HC705UGANG
MC68HC05BD3
8-3
SYNC SIGNAL PROCESSOR
8
8.1.1.2
Separate Horizontal Or Composite Sync Input
Since the input at HSYNC can be either a pure horizontal sync signal or a composite sync signal,
different methodologies are used in polarity correction.
Unlike the polarity correction for VSYNC, both the high pulse and low pulse of the sync signal at
HSYNC are examined. If the pulse, either active high or low, is longer than a certain period (8
μ
s
or 16 t
CYC
), it will be regarded as a long pulse. If there are 8 consecutive low long pulses, the input
sync signal will be confirmed as a positive polarity sync signal, and will be inverted. If there are 8
consecutive high long pulses, it will be confirmed as a negative polarity sync signal.
The operation of this module is also continuous, and the error margin is equal to the period of the
pre-set number (default is 8) of horizontal sync pulses. At power-up or system reset, negative
polarity at input is assumed.
8.1.2
Sync Detection
The sync detector determines whether the incoming sync signal is active. Both sync high and low
pulse widths must be within the specific values to be regarded as active. HDET and VDET flags
will be set if the HSYNC and VSYNC signals are active, respectively.
Figure 8-2
Sync Signal Polarity Correction
Negative polarity pure horizontal sync signal
Positive polarity pure horizontal sync signal
Negative polarity composite sync signal
Positive polarity composite sync signal
TPG
61
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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