CPU32+
MC68360 USER’S MANUAL
Figure 5-28. Functional Model of Instruction Pipeline
When IPIPE1 is low during a clock cycle, it indicates the use of data from IRB on that clock
cycle. IPIPE1 should be sampled by the user on the falling edge of CLKO1. Regardless of
the presence of valid data in IRA or IRL, the contents of IRB are invalidated when IPIPE1 is
asserted. If IRA or IRL contain valid data, the data is copied into IRB (IRA/IRL
IRB), and
the IRB stage is revalidated.
When IPIPE0 is low during a clock cycle, it indicates the start of a new instruction and sub-
sequent replacement of data in IRC. This action causes a full advance of the pipeline (IRB
IRC and IRA/IRL IRB). IRA and/or IRL is refilled during the next instruction fetch bus
cycle.
Data loaded into IRA and IRL propagates automatically through subsequent empty pipeline
stages. Signals that show the progress of instructions through IRB and IRC are necessary
to accurately monitor pipeline operation. These signals are provided by IRA, IRL and IRB
validity bits. When a pipeline advance occurs, the validity bit of the stage being loaded is set,
and the validity bit of the stage supplying the data is negated.
Because instruction execution is not timed to bus activity, IPIPE1–IPIPE0 are synchronized
with the system clock and not the bus.
Figure 5-29 illustrates the timing in relation to the sys-
tem clock.
Figure 5-29. Instruction Pipeline Timing Diagram
I
R
C
DATA
BUS
(31–16)
EXTENSION
WORDS
OPCODES
RESIDUAL
I
R
B
I
R
A
DATA
BUS
(15–0)
I
R
L
IPIPE0
INSTRUCTION
START
EXTENSION
LONG WORD
USED
INSTRUCTION
START
IRB
IRC
CLKO1
IPIPE1
IRA/IRL
IRB
IRA/IRL
IRB
IRA/IRL
IRB
IRC
IRA/IRL
IRB
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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