![](http://datasheet.mmic.net.cn/30000/MC68EN360FE33_datasheet_2368935/MC68EN360FE33_315.png)
System Integration Module (SIM60)
MC68360 USER’S MANUAL
NOTE
An access to a region that has no V-bit set may cause a bus
monitor timeout.
0 = This DRAM/SRAM bank is invalid.
1 = This DRAM/SRAM bank is valid.
NOTE
Following a system reset, the V-bit is set in BR0 if the global chip
select is enabled. See the CONFIG pins for more details.
WP—Write Protection
This bit can restrict write accesses within the address range of a BR. An attempt to write
to the range of addresses specified in a BR that has this bit set can cause the BERR signal
to be asserted by the bus monitor logic (if enabled), causing termination of this cycle.
0 = Both read and write accesses are allowed.
1 = Only read accesses are allowed. The RAS/CS signal, TA, and DSACK will not be
asserted by the QUICC on write cycles to this memory bank. WPER will be set in
the MSTAT register if a write to this memory bank is attempted.
PAREN—Parity Checking Enable
This bit is used to enable checking of parity on either an SRAM or DRAM bank.
0 = Parity checking is disabled.
1 = Parity checking is enabled.
NOTE
Parity checking is not possible for asynchronous external mas-
ters.
CSNTQ—CS Negate Timing QUICC (SRAM Bank Only)
This bit is used to determine when CS is negated during an internal QUICC or external
QUICC/MC68030-type bus master write cycle. This is helpful to meet address/data hold
0 = CS is negated normally (as late as possible).
1 = CS is negated one phase earlier, but the cycle length is not affected.
NOTE
CSNTQ is ignored for an SRAM cycle by an external master if
the SYNC bit is cleared. CSNTQ = 1 is not valid for external
DSACK assertion
CSNT40—CS Negate Timing MC68EC040 (SRAM Bank Only)
This bit is used to determine when CS is negated during an MC68EC040 write cycle. This
is helpful to meet address/data hold time requirements (see
Figure 6-15).0 = CS is negated normally (as late as possible).
1 = CS is negated one phase earlier, but the cycle length is not affected.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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