System Integration Module (SIM60)
MC68360 USER’S MANUAL
SW—Software Watchdog Reset
1 = The last reset was caused by the software watchdog circuit.
DBF—Double Bus Fault Monitor Reset
1 = The last reset was caused by the double bus fault monitor.
Bit 3—Reserved
LOC—Loss of Clock Reset
1 = The last reset was caused by a loss of frequency reference to the clock sub-mod-
ule. This reset can only occur if the RSTEN bit in the clock sub-module is set and
the VCO is enabled.
SRST—Soft Reset
1 = The last reset was caused by the CPU32+ executing a RESET instruction. The RE-
SET instruction does not load a reset vector or affect any internal CPU32+ regis-
ters or SIM60 configuration registers, but does reset external devices and other
internal modules. See Section 3 QUICC Memory Map for a listing of registers af-
fected by the hard reset. This bit is not valid in CPU disable mode.
SRSTP—Soft Reset Pin
1 = The last reset was caused by an external signal driving RESETS. See Section 3
QUICC Memory Map for a listing of registers affected by the soft reset.
6.9.3.4 SOFTWARE WATCHDOG INTERRUPT VECTOR REGISTER (SWIV). The SWIV
contains the 8-bit vector that is returned by the SIM60 during an interrupt acknowledge cycle
in response to an interrupt generated by the SWT. This register can be read or written at any
time. This register is set to the uninitialized vector, $0F, at reset.
SUPERVISOR ONLY
6.9.3.5 SYSTEM PROTECTION CONTROL REGISTER (SYPCR). The SYPCR controls
the system monitors, the prescaler for the SWT, and the bus monitor timing. This register
can be read at any time, but can be written only once after system reset.
SUPERVISOR ONLY
7
6543210
SWIV7
SWIV6
SWIV5
SWIV4
SWIV3
SWIV2
SWIV1
SWIV0
RESET:
0
0001111
7
6543210
SWE
SWRI
SWT1
SWT0
DBFE
BME
BMT1
BMT0
RESET:
11
MODCK
1
MODCK
10000
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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