Applications
9-84
MC68360 USER’S MANUAL
9.8.2.4 EEPROM. Figure 9-31 shows the interface to an EEPROM device to give a small
amount of nonvolatile storage. In this case a byte-wide EEPROM bank is defined to mini-
mize cost. If the port size of the chip select is selected to be 8-bits, then each byte of the
EEPROM may be accessed in succession. The CS4 pin should be programmed to respond
to an 8K byte area in this design.
Only one byte should be written at a time. After a write is made, software is responsible for
waiting the appropriate time (e.g. 10 ms) or for doing data polling to see if the newly written
data byte is correct.
Figure 9-31. 8-Kbyte EEPROM Bank—8 Bits Wide
9.8.2.5 DRAM SIMM. Figure 9-32 shows the interface to an MCM32100S DRAM single in-
line memory module (SIMM). Both the MC68EC030 and the QUICC can access the DRAM.
When the QUICC is a slave to an external MC68EC030, the address multiplexing for the
DRAM must be done externally to the QUICC, which is accomplished in the three F157 mul-
tiplexers. The external address multiplexing scheme is very simple and allows page mode
operation to be provided for the MC68EC030, if desired. This multiplexing scheme exter-
nally provides, the same multiplexing method that the QUICC implements internally.
NOTE
This multiplexing scheme allows the use of page mode, but re-
quires hardware modification if larger SIMMs are to be used on
the board. If the user is interested in the latter, rather than the
WE (Write)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE (Enable)
OE
2864
8K
× 8
EEPROM
BYTE
PORT SIZE
A12–A0
D31–D24
SYSTEM BUS AND
QUICC-GENERATED SIGNALS
CS4
R/W
WE3
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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