CPU32+
5-8
MC68360 USER’S MANUAL
Figure 5-5. Status Register
5.3 INSTRUCTION SET
The following paragaphs describe the CPU32+ instruction set. A description of the instruc-
tion format, the operands used by the instructions, and a summary of the instructions by cat-
egory are included. Complete programming information is provided in the M68000PM/AD,
M68000 Family Programmer’s Reference Manual.
The CPU32+ instructions include machine functions for all the following operations:
Data Movement
Arithmetic Operations
Logical Operations
Shifts and Rotates
Bit Manipulation
Conditionals and Branches
System Control
The large instruction set encompasses a complete range of capabilities and, combined with
the enhanced addressing modes, provides a flexible base for program development.
The instruction set of the CPU32+ is very similar to that of the MC68020 (see
Table 5-1).The following M68020 instructions are not implemented on the CPU32+:
BFxx
— Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU,
BFFFO, BFINS, BFSET, BFTST)
CALLM, RTM — Call Module, Return Module
CAS, CAS2
— Compare and Set (Read-Modify-Write Instructions)
cpxxx
— Coprocessor Instructions (cpBcc, cpDBcc, cpGEN, cpRESTORE,
cpSAVE, cpScc, cpTRAPcc)
PACK, UNPK — Pack, Unpack BCD Instructions
The CPU32+ traps on unimplemented instructions or illegal effective addressing modes,
allowing user-supplied code to emulate unimplemented capabilities or to define special-pur-
pose functions. However, Motorola reserves the right to use all currently unimplemented
instruction operation codes for future M68000 core enhancements.
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2
1
0
T1
T0
S
0
I2
I1
I0
0
X
N
Z
V
C
EXTEND
NEGATIVE
ZERO
OVERFLOW
CARRY
INTERRUPT
PRIORITY MASK
SUPERVISOR/USER
STATE
TRACE
ENABLE
SYSTEM BYTE
USER BYTE
(CONDITION CODE REGISTER)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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