System Integration Module (SIM60)
MC68360 USER’S MANUAL
RRQEN—RISC Request Enable
This bit specifies if the general system clock returns to high frequency (defined by the
DFNH bits)
while the CPM RISC controller is not idle.
0 = Remain in lower frequency (defined by DFNL) even if the RISC controller is not
idle.
1 = Switch to the high frequency (defined by DFNH) when the RISC controller needs
to execute a routine.
DFNL—Division Factor Lowest Frequency
These bits are required in two cases: 1) to reduce the general system clock to a frequency
lower than that which can be obtained in DFNH and 2) to automatically switch between
how to automatically switch between the DFNH rate and the DFNL rate.
The user may load these bits with the desired divide value, and then set the CSRC bit to
change the frequency. Changing the value of the these bits will never cause a loss-of-lock
condition. These bits are cleared by a hardware reset.
000 = Divide by 2
001 = Divide by 4
010 = Divide by 8
011 = Divide by 16
100 = Divide by 32
101 = Divide by 64
110 = Reserved
111 = Divide by 256
DFNH—Division Factor High Frequency
Changing the value of these bits will never cause a loss-of-lock condition. These bits are
cleared (divide by 1) by a hardware reset. The default value is divide by 1 (VCO/2), which
is 25 MHz in a 25-MHz system. The user may write the DFNH bits at any time to change
the general system clock rate.
tween the DFNH rate and the DFNL rate.
000 = Divide by 1 (normal operation of general system clock when CSRC = 0)
001 = Divide by 2
010 = Divide by 4
011 = Divide by 8
100 = Divide by 16
101 = Divide by 32
110 = Divide by 64
111 = Reserved
CSRC—Clock Source Bit
The CSRC bit specifies whether the general system clock is determined by the DFNH or
the DFNL bits. Setting this bit switches the general system clock to the DFNL value (i.e.,
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Freescale Semiconductor, Inc.
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