CPU32+
5-100
MC68360 USER’S MANUAL
5.7.2.13 EXCEPTION-RELATED INSTRUCTIONS AND OPERATIONS. The
exception-
related instructions and operations table indicates the number of clock periods needed for
the processor to perform the specified exception-related actions. No additional tables are
needed to calculate total effective execution time for these instructions. The total number of
clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are
included in the total clock cycle number. All timing data assumes two-clock reads and writes.
Instruction
Head
Tail
Cycles
BKPT (Acknowledged)
0
14(1/0/0)
BKPT (Bus Error)
0
2
35(3/2/4)
Breakpoint (Acknowledged)
0
10(1/0/0)
Breakpoint (Bus Error)
0
2
42(3/2/6)
Interrupt
0
2
30(3/2/4)
RESET
0
518(0/1/0)
STOP
2
0
12(0/1/0)
LPSTOP
3
2
25(0/3/1)
Divide-by-Zero
0
2
36(2/2/6)
Trace
0
2
36(2/2/6)
TRAP #
4
2
29(2/2/4)
ILLEGAL
0
2
25(2/2/4)
A-line
0
2
25(2/2/4)
F-line (First word illegal)
0
2
25(2/2/4)
F-line (Second word illegal) ea = Rn
1
2
31(2/3/4)
F-line (Second word illegal) ea
≠ Rn (Save)
1
3(0/1/0)
F-line (Second word illegal) ea
≠ Rn (Op)
4
2
29(2/2/4)
Privileged
0
2
25(2/2/4)
TRAPcc (trap)
2
38(2/2/6)
TRAPcc (no trap)
2
0
4(0/1/0)
TRAPcc.W (trap)
2
38(2/2/6)
TRAPcc.W (no trap)
0
4(0/2/0)
TRAPcc.L (trap)
0
2
38(2/2/6)
TRAPcc.L (no trap)
0
6(0/3/0)
TRAPV (trap)
2
38(2/2/6)
TRAPV (no trap)
2
0
4(0/1/0)
= Minimum interrupt acknowledge cycle time is assumed to be three clocks.
Timing is calculated with the CPU32+ in 16-bit mode.
NOTE:
The F-line (second word illegal) operation involves a save step which other
operations do not have. To calculate the total operation time, calculate the save, the calculate
EA, and the operation execution times, and combine in the order
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.