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Bus Operation
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MC68360 USER’S MANUAL
master at the same time, the one having the highest priority becomes bus master first. The
sequence of the protocol in normal slave mode is as follows:
1. The QUICC asserts BR.
2. The QUICC waits for the assertion of BG and the negation of BGACK to indicate that
the bus is available.
3. The QUICC asserts BGACK to indicate that it has assumed the bus.
The state machine for the normal slave mode arbitration is shown in
Figure 4-38.Figure 4-38. Slave Mode Bus Arbitration State Machine
In 68040 companion mode, the QUICC changes its bus arbitration sequence to match that
needed by the 68040. It is as follows:
1. The QUICC asserts BG continuously whenever the QUICC does not need the bus.
2. When the QUICC needs the bus, and the 68040 is not requesting the bus, it will deas-
sert BG from the 68040 and assert BB to indicate that it has assumed the bus. If the
68040 then requests the bus using the BR pin, while the QUICC is asserting BB, the
BR040ID bits in the MCR will be used to determine if the 68040 has a high enough bus
request priority to cause the QUICC to give up the bus (i.e. deassert BB and assert
BG.)
IDLE
QUICC
WAITING FOR
BUS
QUICC
OWNS BUS
BR
NEGATED
BR
ASSERTED
EXTERNAL
BUS IDLE
QUICC REQUIRES EXTERNAL BUS
NOTE: BGACK is only asserted by QUICC during the state "QUICC Owns Bus", otherwise BGACK is
three-stated by the QUICC.
BG = 1
BG = 0
BR NEGATED
BGACK
ASSERTED
QUICC STILL NEEDS BUS
HALT IS ASSERTED AND DRAM REFRESH
DOES NOT REQUIRE EXTERNAL BUS
QUICC NO LONGER NEEDS BUS
OR
HALT ASSERTED AND DRAM
REFRESH DOES NOT NEED BUS
EXTERNAL MASTER ACCESS TO DUAL PORT RAM
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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