System Integration Module (SIM60)
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MC68360 USER’S MANUAL
4. AS5—mask supervisor data address space (FC3–FC0=0101)
5. AS4—mask Motorola reserved address space (FC3–FC0=0100)
6. AS3—mask user reserved address space (FC3–FC0=0011)
7. AS2—mask user program address space (FC3–FC0=0010)
8. AS1—mask user data address space (FC3–FC0=0001)
9. AS0—mask Motorola reserved address space (FC3–FC0=0000)
The address space bits for 040 type MPU are:
1. AS8—no relevance for 040 cycles
2. AS7—acknowledge access (TT1-TT0=11)
3. AS6—supervisor code access (TT1-TT0=00, TM2-TM0=110)
4. AS5—supervisor data access (TT1-TT0=00, TM2-TM0=101)
5. AS4—MMU table search code access (TT1-TT0=00, TM2-TM0=100)
6. AS3—MMU table search data access (TT1-TT0=00, TM2-TM0=011)
7. AS2—user code access (TT1-TT0=00, TM2-TM0=010)
8. AS1—user data access (TT1-TT0=00, TM2-TM0=001)
9. AS0—data cache push access (TT1-TT0=00, TM2-TM0=000)
NOTE
The user should mask off AS7, AS4, AS3 and AS1 to prevent
unwanted access to the QUICC internal dual port RAM (DPR).
For example, AS7 should be masked out so that the IACK cycle
will not cause an access to the DPR.
For each address space bit:
1 = Mask this address space from the internal module selection. The bus cycle goes
external.
0 = Decode for the internal module block.
V—Valid
This bit indicates when the contents of the MBAR are valid. The base address value is not
used; therefore, all internal module registers are not accessible until the V-bit is set.
0 = Contents not valid.
1 = Contents valid.
NOTE
When working in the CPU enable mode, an access to this regis-
ter does not affect external space since the cycle is not run ex-
ternally.
MBAR can be read using the following code. Register D0 will contain the value of MBAR.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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