CPU32+
MC68360 USER’S MANUAL
Enhanced Breakpoint Instruction
Trace on Change of Flow
Table Lookup and Interpolate (TBL) Instruction
LPSTOP Instruction
Hardware BKPT Signal, Background Mode
Fully Static Implementation
A block diagram of the CPU32+ is shown in
Figure 5-1. The major blocks depicted operate
in a highly independent fashion that maximizes concurrences of operation while managing
the essential synchronization of instruction execution and bus operation. The bus controller
loads instructions from the data bus into the decode unit. The sequencer and control unit
provide overall chip control by managing the internal buses, registers, and functions of the
execution unit.
Figure 5-1. CPU32+ Block Diagram
5.1.2 Loop Mode Instruction Execution
The CPU32+ has several features that provide efficient execution of program loops. One of
these features is the DBcc looping primitive instruction. To increase the performance of the
CPU32+, a loop mode has been added to the processor. The loop mode is used by any sin-
gle-word instruction that does not change the program flow. Loop mode is implemented in
conjunction with the DBcc instruction.
Figure 5-2 shows the required form of an instruction
loop for the processor to enter loop mode.
The loop mode is entered when the DBcc instruction is executed and the loop displacement
is –4. Once in loop mode, the processor performs only the data cycles associated with the
instruction and suppresses all instruction fetches. The termination condition and count are
checked after each execution of the data operations of the looped instruction. The CPU32+
automatically exits the loop mode during interrupts or other exceptions.
BUS CONTROL
INSTRUCTION
PREFETCH
AND
DECODE
EXECUTION
UNIT
SEQUENCER
CONTROL
UNIT
BUS
CONTROL
ADDRESS
BUS
DATA BUS
16
32
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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