System Integration Module (SIM60)
MC68360 USER’S MANUAL
NOTE
When the SWP and SWT bits are modified to select a software
timeout other than the default, the software service sequence
($55 followed by $AA written to the software service register)
must be performed before the new timeout period takes effect.
DBFE—Double Bus Fault Monitor Enable
1 = Enable the double bus fault monitor function. (Default)
0 = Disable the double bus fault monitor function.
BME—Bus Monitor External Enable
0 = Enable bus monitor function for the external bus cycles.
1 = Disable bus monitor function for the external bus cycles. (Default)
BMT1–BMT0—Bus Monitor Timing
These bits select the timeout period for the bus monitor (see
Table 6-5).6.9.3.6 PERIODIC INTERRUPT CONTROL REGISTER (PICR). The PICR contains the
interrupt level and the vector number for the periodic interrupt request. This register can be
read or written at any time. Bits 15–11 are unimplemented and always return zero; a write
to these bits has no effect.
SUPERVISOR ONLY
PIRQL2–PIRQL0—Periodic Interrupt Request Level
These bits contain the periodic interrupt request level.
Table 6-6 lists which interrupt re-
quest level is asserted during an interrupt acknowledge cycle when a periodic interrupt is
generated. The PIT continues to run when the interrupt is disabled.
NOTE
Use caution with a level 7 interrupt encoding due to the SIM60
Table 6-5. BMT Encoding
BMT1
BMT0
Bus Monitor Timeout Period
0
1K System Clocks (CLKO1 Clocks)
0
1
512 System Clocks
1
0
256 System Clocks
1
128 System Clocks
15
14
13
12
11
10
9876543210
0
0000
PIRQL2 PIRQL1 PIRQL0
PIV7
PIV6
PIV5
PIV4
PIV3
PIV2
PIV1
PIV0
RESET:
0
000000000001111
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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