System Integration Module (SIM60)
6-14
MC68360 USER’S MANUAL
divided prior to being used by any QUICC on-chip module). Furthermore, the divide-by-128
function allows the value of the final system frequency to be chosen with much greater pre-
cision, since it is a multiple of ~32 kHz rather than a multiple of ~4 MHz.
The choice of whether to use the divide-by-128 function is made with the MODCK1–
MODCK0 pins. This resulting frequency is called CLKIN.
Figure 6-6. External Components
6.5.3 Phase-Locked Loop (PLL)
The PLL takes the CLKIN frequency and outputs a high-frequency source used to derive the
general system frequency of the QUICC. The PLL is comprised of a phase detector, loop
filter, voltage-controlled oscillator (VCO), and multiplication block. The VCO output can be
as high as 50 MHz for a 25-MHz QUICC.
The PLL’s main functions are frequency multiplication and skew elimination.
6.5.3.1 FREQUENCY MULTIPLICATION. The PLL can multiply the CLKIN input frequency
by any integer between 1 and 4096. The output of the VCO is twice the QUICC system fre-
quency after reset.
If a low frequency crystal is chosen (e.g., ~32 kHz), the multiplier defaults to 401, giving a
2
× VCO output of ~26 MHz and an initial general system clock of ~13 MHz. The multiplica-
tion factor may then be changed to the desired value by writing the MF11–MF0 bits in the
PLLCR. When the PLL multiplier is modified in software, the PLL will lose lock, and the
clocking to the QUICC will stop until lock is regained (worst case is 2500 clocks; typical case
ing lock.
EXTAL
CRYSTAL
OSCILLATOR
XTAL
XFC PIN
VCCSYN
XFC
390nF
0.01
F
0.1
F
NOTE:
1. Must be low-leakage capacitor. See Section 10 Electrical Characteristics for recommended values.
2. Values are for 32 kHz crystal and may vary due to capacitance on PCB.
20 pF
20 M
330
K
1
CLKO1
CLOCK
GENERATION
CLKO2
VCCCLK
GNDCLK
0.1
F
GNDSYN
VCCSYN
CRYSTAL 2
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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